The Experts below are selected from a list of 300 Experts worldwide ranked by ideXlab platform
A. Bounceur - One of the best experts on this subject based on the ideXlab platform.
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A 0.18 /spl mu/m CMOS implementation of on-chip analogue Test Signal generation from digital Test patterns
Proceedings Design Automation and Test in Europe Conference and Exhibition, 2004Co-Authors: L. Rolindez, G. Prenat, A. BounceurAbstract:The Test of analogue and mixed-Signal (AMS) cores requires the use of expensive AMS Testers and accessibility to internal analogue nodes. The Test cost can be considerably reduced by the use of built-in-self-Test (BIST) techniques. One of these techniques consists of generating analogue Test Signals from digital Test patterns (obtained via /spl Sigma//spl Delta/ modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. This paper presents an implementation of the analogue Test Signal generation part that includes programmability of the circuit blocks, leading to an improvement of performance and a reduction of circuit size with respect to previous approaches. A 0.18 /spl mu/m CMOS circuit has been designed and fabricated, allowing the generation of Test Signals ranging from 10 Hz to 1 MHz.
L. Rolindez - One of the best experts on this subject based on the ideXlab platform.
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A 0.18 /spl mu/m CMOS implementation of on-chip analogue Test Signal generation from digital Test patterns
Proceedings Design Automation and Test in Europe Conference and Exhibition, 2004Co-Authors: L. Rolindez, G. Prenat, A. BounceurAbstract:The Test of analogue and mixed-Signal (AMS) cores requires the use of expensive AMS Testers and accessibility to internal analogue nodes. The Test cost can be considerably reduced by the use of built-in-self-Test (BIST) techniques. One of these techniques consists of generating analogue Test Signals from digital Test patterns (obtained via /spl Sigma//spl Delta/ modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. This paper presents an implementation of the analogue Test Signal generation part that includes programmability of the circuit blocks, leading to an improvement of performance and a reduction of circuit size with respect to previous approaches. A 0.18 /spl mu/m CMOS circuit has been designed and fabricated, allowing the generation of Test Signals ranging from 10 Hz to 1 MHz.
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An implementation of memory-based on-chip analogue Test Signal generation
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference 2003., 2003Co-Authors: L. Rolindez, C. Domigues, L. RuferAbstract:This paper presents a memory-based on-chip analogue Test Signal generation approach that is suitable for the Test of an analogue and mixed-Signal (AMS) core. This core contains programmable electronic interfaces for acoustic and ultrasound transducers. The Test Signals that must be generated on-chip have only low or moderate frequencies (10 Hz-10 MHz). The Test circuitry designed in a 0.18 /spl mu/m CMOS technology includes a programmable shift-register, a clock divider, and a programmable switched-capacitor filter bank. By controlling the shift-register length and the sampling frequency, the paper shows that high quality single tone Signals can be generated on chip in the band of interest.
Marvin Onabajo - One of the best experts on this subject based on the ideXlab platform.
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A low-power temperature-compensated relaxation oscillator for built-in Test Signal generation
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015Co-Authors: Li Xu, Marvin OnabajoAbstract:An on-chip frequency reference for built-in Testing and calibration applications is presented. The design combines a proportional-to-absolute-temperature (PTAT) current reference and a relaxation oscillator core. A temperature compensation scheme is realized based on the thermal voltage, for which simulations indicate low sensitivity to process variations. The oscillator was designed and simulated in a 130nm CMOS process with a power supply of 1.2V. It generates a 40KHz output and occupies a layout area of 0.025mm2. A temperature coefficient of 101ppm/°C is achieved over the range from -30°C to 85°C. The simulated phase noise is -90dBc/Hz at 10KHz offset.
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Test Signal Generation for the Calibration of Analog Front-End Circuits in Biopotential Measurement Applications
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014Co-Authors: Li Xu, Junpeng Feng, Yuchi Ni, Marvin OnabajoAbstract:A Test Signal generator to calibrate analog front-ends for biopotential measurements is presented. The integrated Signal generator enables detection of the input impedance at the frontend instrumentation amplifier based on current injection and amplitude detection. It can generate picoampere currents while ensuring a high output impedance of 2.9GΩ up to 100Hz. The Test Signal generator was designed and simulated in 0.13μm CMOS technology and it consists of a temperature-compensated relaxation oscillator, a frequency divider, a limiter, and an operational transconductance amplifier. Keywords—Test Signal generation; self-calibrated analog front-end; input capacitance cancellation; low-transconductance OTA; dry-contact electrode measurement technique.
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Test Signal generation for the calibration of analog front-end circuits in biopotential measurement applications
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014Co-Authors: Li Xu, Junpeng Feng, Yuchi Ni, Marvin OnabajoAbstract:A Test Signal generator to calibrate analog front-ends for biopotential measurements is presented. The integrated Signal generator enables detection of the input impedance at the front-end instrumentation amplifier based on current injection and amplitude detection. It can generate picoampere currents while ensuring a high output impedance of 2.9GΩ up to 100Hz. The Test Signal generator was designed and simulated in 0.13μm CMOS technology and it consists of a temperature-compensated relaxation oscillator, a frequency divider, a limiter, and an operational transconductance amplifier.
G. Prenat - One of the best experts on this subject based on the ideXlab platform.
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A 0.18 /spl mu/m CMOS implementation of on-chip analogue Test Signal generation from digital Test patterns
Proceedings Design Automation and Test in Europe Conference and Exhibition, 2004Co-Authors: L. Rolindez, G. Prenat, A. BounceurAbstract:The Test of analogue and mixed-Signal (AMS) cores requires the use of expensive AMS Testers and accessibility to internal analogue nodes. The Test cost can be considerably reduced by the use of built-in-self-Test (BIST) techniques. One of these techniques consists of generating analogue Test Signals from digital Test patterns (obtained via /spl Sigma//spl Delta/ modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. This paper presents an implementation of the analogue Test Signal generation part that includes programmability of the circuit blocks, leading to an improvement of performance and a reduction of circuit size with respect to previous approaches. A 0.18 /spl mu/m CMOS circuit has been designed and fabricated, allowing the generation of Test Signals ranging from 10 Hz to 1 MHz.
A. T. Shenton - One of the best experts on this subject based on the ideXlab platform.
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Constrained Optimal Test Signal Design for Improved Prediction Error
IEEE Transactions on Automation Science and Engineering, 2014Co-Authors: K. Fang, A. T. ShentonAbstract:This paper presents a new efficient methodology for the optimal design of discrete Test Signals in black-box dynamic nonlinear system identification. The approach is based on a new criterion which weights the parameter covariances with the magnitudes of output sensitivities both to reduce the parameter estimation error and also allow the optimization of the output fitness. Optimization using this criterion has a low computational cost and in the case that the regressors are well chosen the performance index approximates that of the I-optimality criterion and results in high output fitness. The new method allows for the efficient use of numerical constrained global optimization algorithms to be applied to magnitude and rate constraints on system inputs and outputs, which are essential considerations in experimental applications. The approach should thus be employable as a component of an iterative bootstrapping procedure for experimental system identification subject to safe operating limits. The approach is applied to the black-box nonlinear multiple-input multiple-output identification of an automotive engine-fueling model as a benchmark. The results are compared with those obtained by other computationally efficient methods of both nonoptimal and optimal type. Statistical validation of the results shows that the design method using the new criterion gives Test Signals satisfying the required operational constraints which have superior outcomes in output prediction fit.
