The Experts below are selected from a list of 570321 Experts worldwide ranked by ideXlab platform
K.l. Young - One of the best experts on this subject based on the ideXlab platform.
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field configurable Test Structure array fc tsa enabling design for monitor model and manufacturability
IEEE Transactions on Semiconductor Manufacturing, 2008Co-Authors: Kelvin Y.y. Doong, L.j. Hung, T J Bordelon, Chienchih Liao, S P S Ho, Sunnys Hsieh, K.l. YoungAbstract:This paper describes a common framework of Test chip design for logic technology development and routine process monitoring, referred to as a field-configurable Test Structure array (FC-TSA), which can accommodate and Test various types of Test Structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-Test within the Test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various Test Structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The measurements of a set of transistor and process monitor Test Structures are reviewed and corresponding models discussed.
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field configurable Test Structure array fc tsa enabling design for monitor model and manufacturability
International Conference on Microelectronic Test Structures, 2006Co-Authors: Kelvin Y.y. Doong, L.j. Hung, Sunnys Hsieh, J Bordelon, Kehjeng Chang, C C Liao, R S Ho, K.l. YoungAbstract:This work is designated to provide a common frame work of Test chip design for technology development and process routine monitor, called as field-configurable Test Structure array (FC-TSA), which can accommodate and Test the various types of Test Structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-Test in a Test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various Test Structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array Test Structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor Test Structures are reviewed and corresponding models are discussed.
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Library-based process Test vehicle design framework
Design and Process Integration for Microelectronic Manufacturing, 2003Co-Authors: Kelvin Y.y. Doong, Susan Ho, L.j. Hung, K.l. YoungAbstract:This work describes a Test vehicle design framework, which minimizes the discrepancy among design rule set, Tests Structure design and Testing plan. The framework is composed of the symbolic design rule set, Parametereized-Device, Test Structure generator, and Test vehicle generator. An approach for simplification and consolidation of Test Structure is proposed to derive the concise Test Structure library. Finally, implementation of Test vehicle is presented.
Masayoshi Nakashima - One of the best experts on this subject based on the ideXlab platform.
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seismic damage detection of a full scale shaking table Test Structure
Journal of Structural Engineering-asce, 2011Co-Authors: Gregory L Fenves, Kouichi Kajiwara, Masayoshi NakashimaAbstract:A series of full-scale Tests was conducted on the E-Defense shaking table facilities in Japan to simulate various levels of realistic seismic damage in a high-rise structural steel building. During the shaking table Tests, the specimen experienced damage of the concrete slabs, beam-to-column connections, and nonstructural walls. The densely recorded Test data of global and local structural deformation and the extensive acceleration records provide a unique benchmark case for evaluating the effectiveness of vibration-based damage diagnosis methods. Dynamic properties of the specimen were extracted from floor accelerations under the white noise excitations by the frequency response function curve-fitting method and autoregressive with exogenous term method. The natural frequencies of the Structure decreased on average 4.1, 5.4, and 11.9% after three levels of seismic excitation, respectively, because of increasing extent of structural and nonstructural damage. The analysis of the vibration data shows that t...
Kelvin Y.y. Doong - One of the best experts on this subject based on the ideXlab platform.
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field configurable Test Structure array fc tsa enabling design for monitor model and manufacturability
IEEE Transactions on Semiconductor Manufacturing, 2008Co-Authors: Kelvin Y.y. Doong, L.j. Hung, T J Bordelon, Chienchih Liao, S P S Ho, Sunnys Hsieh, K.l. YoungAbstract:This paper describes a common framework of Test chip design for logic technology development and routine process monitoring, referred to as a field-configurable Test Structure array (FC-TSA), which can accommodate and Test various types of Test Structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-Test within the Test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various Test Structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The measurements of a set of transistor and process monitor Test Structures are reviewed and corresponding models discussed.
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field configurable Test Structure array fc tsa enabling design for monitor model and manufacturability
International Conference on Microelectronic Test Structures, 2006Co-Authors: Kelvin Y.y. Doong, L.j. Hung, Sunnys Hsieh, J Bordelon, Kehjeng Chang, C C Liao, R S Ho, K.l. YoungAbstract:This work is designated to provide a common frame work of Test chip design for technology development and process routine monitor, called as field-configurable Test Structure array (FC-TSA), which can accommodate and Test the various types of Test Structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-Test in a Test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various Test Structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array Test Structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor Test Structures are reviewed and corresponding models are discussed.
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Library-based process Test vehicle design framework
Design and Process Integration for Microelectronic Manufacturing, 2003Co-Authors: Kelvin Y.y. Doong, Susan Ho, L.j. Hung, K.l. YoungAbstract:This work describes a Test vehicle design framework, which minimizes the discrepancy among design rule set, Tests Structure design and Testing plan. The framework is composed of the symbolic design rule set, Parametereized-Device, Test Structure generator, and Test vehicle generator. An approach for simplification and consolidation of Test Structure is proposed to derive the concise Test Structure library. Finally, implementation of Test vehicle is presented.
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Design and simulation of addressable failure site Test Structure for IC process control monitor
1999 International Symposium on VLSI Technology Systems and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453), 1999Co-Authors: Kelvin Y.y. Doong, Jye-yen ChengAbstract:A novel Test Structure to ensure failure addressable and high-density Test Structure of semiconductor process control monitor with a limited number of contact pads required for electrical Test is described. The placement and routing scheme requires only two levels of conductive layers, and provides the maximum number of bridging and continuity Test Structure units. A graph model is developed to manifest the spatial configuration of Test Structure units and simplify the complexity of fault detection. Also, a generic algorithm of multi-fault detection was developed.
Khalid M Mosalam - One of the best experts on this subject based on the ideXlab platform.
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shake table experiment on reinforced concrete Structure containing masonry infill wall
Earthquake Engineering & Structural Dynamics, 2006Co-Authors: Alidad Hashemi, Khalid M MosalamAbstract:A hypothetical 5-storey prototype Structure with reinforced concrete (RC) frame and unreinforced masonry (URM) wall is considered. The paper focuses on a shake-table experiment conducted on a subStructure of this prototype consisting of the middle bays of its first storey. A Test Structure is constructed to represent the selected subStructure and the relationship between demand parameters of the Test Structure and those of the prototype Structure is established using computational modelling. The dynamic properties of the Test Structure are determined using a number of preliminary Tests before performing the shake-table experiments. Based on these Tests and results obtained from computational modelling of the Test Structure, the Test ground motions and the sequence of shakings are determined. The results of the shake-table Tests in terms of the global and local responses and the effects of the URM infill wall on the structural behaviour and the dynamic properties of the RC Test Structure are presented. Finally, the Test results are compared to analytical ones obtained from further computational modelling of the Test Structure subjected to the measured shake-table accelerations. Copyright © 2006 John Wiley & Sons, Ltd.
Gregory L Fenves - One of the best experts on this subject based on the ideXlab platform.
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seismic damage detection of a full scale shaking table Test Structure
Journal of Structural Engineering-asce, 2011Co-Authors: Gregory L Fenves, Kouichi Kajiwara, Masayoshi NakashimaAbstract:A series of full-scale Tests was conducted on the E-Defense shaking table facilities in Japan to simulate various levels of realistic seismic damage in a high-rise structural steel building. During the shaking table Tests, the specimen experienced damage of the concrete slabs, beam-to-column connections, and nonstructural walls. The densely recorded Test data of global and local structural deformation and the extensive acceleration records provide a unique benchmark case for evaluating the effectiveness of vibration-based damage diagnosis methods. Dynamic properties of the specimen were extracted from floor accelerations under the white noise excitations by the frequency response function curve-fitting method and autoregressive with exogenous term method. The natural frequencies of the Structure decreased on average 4.1, 5.4, and 11.9% after three levels of seismic excitation, respectively, because of increasing extent of structural and nonstructural damage. The analysis of the vibration data shows that t...
