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Rahman Mostafizur - One of the best experts on this subject based on the ideXlab platform.

  • Thermal Management in Fine-Grained 3-D Integrated Circuits
    2018
    Co-Authors: Iqbal, Md Arif, Macha, Naveen Kumar, Danesh Wafi, Hossain Sehtab, Rahman Mostafizur
    Abstract:

    For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of Thermal management at all levels of integration [4] as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we investigate the Thermal profile for transistor level 3-D integration approaches through finite element based modeling. Additionally, we propose generic physical level heat management features for such transistor level 3-D integration and show their application through detailed Thermal modeling and simulations. These features include a Thermal Junction and heat conducting nano pillar. The heat Junction is a specialized Junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conJunction with the Junction, our proposed Thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. Such structures are generic and is applicable to any transistor level 3-D integration approaches. We perform 3-D finite element based analysis to capture both static and transient Thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that without any heat extraction feature, temperature for 3-D integrated circuits increased by almost 100K-200K. However, proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.Comment: 9 Page

Sushumna Iruvanti - One of the best experts on this subject based on the ideXlab platform.

  • predicting thermo mechanical degradation of first level Thermal interface materials tims in flip chip electronic packages
    Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2014
    Co-Authors: Tuhin Sinha, Jeffery A Zitz, Rebecca N Wagner, Sushumna Iruvanti
    Abstract:

    Ensuring adequate Thermal performance is essential for the reliable operation of flip-chip electronic packages. Thermal interface materials (TIMs), applied between the die and a heat spreader form a crucial Thermal Junction between the first level package and external cooling mechanisms such as heat-sinks and cooling fans. Selection of a good TIM is dependent not only on its Thermal properties but also on its ability to withstand mechanical stresses in an electronic package. In the past, FEM models have been applied to obtain the stresses and strains in the TIM using time-independent analysis. However, there has only been limited work in extending these models to predict the damage (both mechanical and Thermal) in a TIM during thermo-cyclic loading. Our current work presents a technique to predict the Thermal damage in TIMs over cyclic loading. Calibrated finite element analysis models have been created to predict accurate TIM strains in Thermal test-vehicles. These predicted mechanical strains are then correlated with experimentally observed Thermal degradation and finally, a phenomenological model is developed which predicts the Thermal performance of an electronic package during cyclic loading.

Iqbal, Md Arif - One of the best experts on this subject based on the ideXlab platform.

  • Thermal Management in Fine-Grained 3-D Integrated Circuits
    2018
    Co-Authors: Iqbal, Md Arif, Macha, Naveen Kumar, Danesh Wafi, Hossain Sehtab, Rahman Mostafizur
    Abstract:

    For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of Thermal management at all levels of integration [4] as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we investigate the Thermal profile for transistor level 3-D integration approaches through finite element based modeling. Additionally, we propose generic physical level heat management features for such transistor level 3-D integration and show their application through detailed Thermal modeling and simulations. These features include a Thermal Junction and heat conducting nano pillar. The heat Junction is a specialized Junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conJunction with the Junction, our proposed Thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. Such structures are generic and is applicable to any transistor level 3-D integration approaches. We perform 3-D finite element based analysis to capture both static and transient Thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that without any heat extraction feature, temperature for 3-D integrated circuits increased by almost 100K-200K. However, proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.Comment: 9 Page

Tuhin Sinha - One of the best experts on this subject based on the ideXlab platform.

  • predicting thermo mechanical degradation of first level Thermal interface materials tims in flip chip electronic packages
    Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2014
    Co-Authors: Tuhin Sinha, Jeffery A Zitz, Rebecca N Wagner, Sushumna Iruvanti
    Abstract:

    Ensuring adequate Thermal performance is essential for the reliable operation of flip-chip electronic packages. Thermal interface materials (TIMs), applied between the die and a heat spreader form a crucial Thermal Junction between the first level package and external cooling mechanisms such as heat-sinks and cooling fans. Selection of a good TIM is dependent not only on its Thermal properties but also on its ability to withstand mechanical stresses in an electronic package. In the past, FEM models have been applied to obtain the stresses and strains in the TIM using time-independent analysis. However, there has only been limited work in extending these models to predict the damage (both mechanical and Thermal) in a TIM during thermo-cyclic loading. Our current work presents a technique to predict the Thermal damage in TIMs over cyclic loading. Calibrated finite element analysis models have been created to predict accurate TIM strains in Thermal test-vehicles. These predicted mechanical strains are then correlated with experimentally observed Thermal degradation and finally, a phenomenological model is developed which predicts the Thermal performance of an electronic package during cyclic loading.

Danesh Wafi - One of the best experts on this subject based on the ideXlab platform.

  • Thermal Management in Fine-Grained 3-D Integrated Circuits
    2018
    Co-Authors: Iqbal, Md Arif, Macha, Naveen Kumar, Danesh Wafi, Hossain Sehtab, Rahman Mostafizur
    Abstract:

    For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of Thermal management at all levels of integration [4] as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we investigate the Thermal profile for transistor level 3-D integration approaches through finite element based modeling. Additionally, we propose generic physical level heat management features for such transistor level 3-D integration and show their application through detailed Thermal modeling and simulations. These features include a Thermal Junction and heat conducting nano pillar. The heat Junction is a specialized Junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conJunction with the Junction, our proposed Thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. Such structures are generic and is applicable to any transistor level 3-D integration approaches. We perform 3-D finite element based analysis to capture both static and transient Thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that without any heat extraction feature, temperature for 3-D integrated circuits increased by almost 100K-200K. However, proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.Comment: 9 Page