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Robert S. Howell - One of the best experts on this subject based on the ideXlab platform.

  • Reliable Operation of sic jfet subjected to over 2 4 million 1200 v 115 a hard switching events at 150 circ hbox c
    IEEE Electron Device Letters, 2013
    Co-Authors: Victor Veliadis, H. C. Ha, Pavel Borodulin, K Lawson, Stephen B. Bayne, Damian Urciuoli, B Steiner, S. Gupta, Nabil Elhinnawy, Robert S. Howell
    Abstract:

    A requirement for the commercialization of power SiC transistors is their long-term Reliable Operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150°C from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFET's 250-W/cm2 rated current at 150°C. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the p+ gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance RLC circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150°C and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 A/μs, and the pulse FWHM was 1.8 μs. After over 2.4 million hard switch events at 150°C, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate Reliable Operation.

  • Reliable Operation of sic jfet subjected to over 2.4 million 1200-V/115-A hard switching events at 150 °c
    IEEE Electron Device Letters, 2013
    Co-Authors: Victor Veliadis, H. C. Ha, Pavel Borodulin, N. El-hinnawy, K Lawson, Stephen B. Bayne, Damian Urciuoli, B Steiner, S. Gupta, Robert S. Howell
    Abstract:

    A requirement for the commercialization of power SiC transistors is their long-term Reliable Operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150 $^{circ}hbox{C}$ from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFET's 250-$hbox{W}/hbox{cm}^{2}$ rated current at 150 $^{circ}hbox{C}$. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the $hbox{p}^{+}$ gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance $RLC$ circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150 $^{circ}hbox{C}$ and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 $hbox{A}/muhbox{s}$, and the pulse FWHM was 1.8 $muhbox{s}$. After over 2.4 million hard switch events at 150 $^{circ}hbox{C}$, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate Reliable Operation.

  • Reliable Operation of SiC JFET Subjected to Over 2.4 Million 1200-V/115-A Hard Switching Events at 150 $^{\circ}\hbox{C}$
    IEEE Electron Device Letters, 2013
    Co-Authors: Victor Veliadis, H. C. Ha, Pavel Borodulin, N. El-hinnawy, K Lawson, Stephen B. Bayne, Damian Urciuoli, B Steiner, S. Gupta, Robert S. Howell
    Abstract:

    A requirement for the commercialization of power SiC transistors is their long-term Reliable Operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150°C from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFET's 250-W/cm2 rated current at 150°C. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the p+ gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance RLC circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150°C and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 A/μs, and the pulse FWHM was 1.8 μs. After over 2.4 million hard switch events at 150°C, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate Reliable Operation.

G. Tränkle - One of the best experts on this subject based on the ideXlab platform.

Victor Veliadis - One of the best experts on this subject based on the ideXlab platform.

  • Reliable Operation of sic jfet subjected to over 2 4 million 1200 v 115 a hard switching events at 150 circ hbox c
    IEEE Electron Device Letters, 2013
    Co-Authors: Victor Veliadis, H. C. Ha, Pavel Borodulin, K Lawson, Stephen B. Bayne, Damian Urciuoli, B Steiner, S. Gupta, Nabil Elhinnawy, Robert S. Howell
    Abstract:

    A requirement for the commercialization of power SiC transistors is their long-term Reliable Operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150°C from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFET's 250-W/cm2 rated current at 150°C. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the p+ gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance RLC circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150°C and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 A/μs, and the pulse FWHM was 1.8 μs. After over 2.4 million hard switch events at 150°C, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate Reliable Operation.

  • Reliable Operation of sic jfet subjected to over 2.4 million 1200-V/115-A hard switching events at 150 °c
    IEEE Electron Device Letters, 2013
    Co-Authors: Victor Veliadis, H. C. Ha, Pavel Borodulin, N. El-hinnawy, K Lawson, Stephen B. Bayne, Damian Urciuoli, B Steiner, S. Gupta, Robert S. Howell
    Abstract:

    A requirement for the commercialization of power SiC transistors is their long-term Reliable Operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150 $^{circ}hbox{C}$ from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFET's 250-$hbox{W}/hbox{cm}^{2}$ rated current at 150 $^{circ}hbox{C}$. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the $hbox{p}^{+}$ gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance $RLC$ circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150 $^{circ}hbox{C}$ and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 $hbox{A}/muhbox{s}$, and the pulse FWHM was 1.8 $muhbox{s}$. After over 2.4 million hard switch events at 150 $^{circ}hbox{C}$, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate Reliable Operation.

  • Reliable Operation of SiC JFET Subjected to Over 2.4 Million 1200-V/115-A Hard Switching Events at 150 $^{\circ}\hbox{C}$
    IEEE Electron Device Letters, 2013
    Co-Authors: Victor Veliadis, H. C. Ha, Pavel Borodulin, N. El-hinnawy, K Lawson, Stephen B. Bayne, Damian Urciuoli, B Steiner, S. Gupta, Robert S. Howell
    Abstract:

    A requirement for the commercialization of power SiC transistors is their long-term Reliable Operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150°C from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFET's 250-W/cm2 rated current at 150°C. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the p+ gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance RLC circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150°C and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 A/μs, and the pulse FWHM was 1.8 μs. After over 2.4 million hard switch events at 150°C, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate Reliable Operation.

Cristian Garbossa - One of the best experts on this subject based on the ideXlab platform.

  • Control technique for Reliable Operation of the synchronous series capacitor tapped inductor converter
    IEEE Transactions on Power Electronics, 2018
    Co-Authors: Giovanni Bonanno, Luca Corradini, Cristian Garbossa
    Abstract:

    In the context of reducing total CO $_2$ emissions as well as reducing the total copper cable length and weight on cars, automotive manufacturers propose to derive all the supply voltages from a single $\text{48 V}$ bus through high step-down ratio dc–dc converters. The series capacitor tapped inductor (SCTI) converter is a promising topology for efficient single-stage step-down conversion from the $\text{48 V}$ bus. In the synchronous version of the SCTI, however, turn- off of the synchronous rectifier at positive drain-to-source current leads to a voltage spike and to a potential catastrophic failure of the converter. In this paper, a simple control technique is proposed, which prevents the foregoing condition to occur. The approach enables a Reliable Operation of the synchronous SCTI topology without disrupting its main features and advantages, and eliminating the need for additional snubbers, voltage clamps or auxiliary windings. The approach is validated via computer simulations and experimental tests on a $\text{48}$ -to- $\text{1.5}\;\text{V}$ , $\text{4 A}$ SCTI converter prototype.

  • Control technique for Reliable Operation of the synchronous series capacitor tapped inductor converter
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC), 2018
    Co-Authors: Giovanni Bonanno, Luca Corradini, Cristian Garbossa
    Abstract:

    In the context of reducing total CO2 emissions as well as reducing the total copper cable length and weight on cars, automotive manufacturers propose to derive all the supply voltages from a single 48 V bus through high step-down ratio dc-dc converters. The series capacitor tapped inductor (SCTI) converter is a promising topology for efficient single-stage step-down conversion from the 48 V bus. In the synchronous version of the SCTI, however, turn-off of the synchronous rectifier at positive drain-to-source current leads to a voltage spike and to a potential catastrophic failure of the converter. In this paper a simple control technique is proposed which prevents the foregoing condition to occur. The approach enables a Reliable Operation of the synchronous SCTI topology without disrupting its main features and advantages, and eliminating the need for additional snubbers, voltage clamps or auxiliary windings. The approach is validated via computer simulations and experimental tests on a 48 V-to-1.5 V, 4 A SCTI converter prototype.

B. Sumpf - One of the best experts on this subject based on the ideXlab platform.

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