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Yvon Savaria - One of the best experts on this subject based on the ideXlab platform.
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a high speed scalable and programmable Traffic Manager architecture for flow based networking
IEEE Access, 2019Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:In this paper, we present a programmable and scalable Traffic Manager (TM) architecture, targeting requirements of high-speed networking devices, especially in the software-defined networking context. This TM is intended to ease the deployability of new architectures through field-programmable gate array (FPGA) platforms and to make the data plane programmable and scalable. Flow-based networking allows treating Traffic in terms of flows rather than as a simple aggregation of individual packets, which simplifies scheduling and bandwidth allocation for each flow. Programmability brings agility, flexibility, and rapid adaptation to changes, allowing to meet network requirements in real-time. Traffic management with fast queuing and reduced latency plays an important role to support the upcoming 5G cellular communication technology. The proposed TM architecture is coded in C++ and is synthesized with the Vivado High-Level Synthesis tool. This TM is capable of supporting links operating beyond 40 Gb/s, on the ZC706 board and XCVU440-FLGB2377-3-E FPGA device from Xilinx, while achieving 80 Gb/s and 100 Gb/s throughput, respectively. The resulting placed and routed design was tested on the ZC706 board with its embedded ARM processor controlling table updates.
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design of a low latency 40 gb s flow based Traffic Manager using high level synthesis
International Symposium on Circuits and Systems, 2018Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:This paper presents a Traffic Manager architecture targeting to meet today's networking requirements, especially reduced latency, and to support the upcoming 5G technology in the software defined networking context. The proposed Traffic Manager functionalities are policing, scheduling, shaping, and queuing of incoming Traffic (packets). The incoming Traffic is assumed to be a set of flows in a network processing unit. Traffic management imposes constraints on packets to be sent out in such a way to meet the allowed bandwidth quotas for each flow, and enforce desired quality of service (QoS) targets. The FPGA prototyped architecture is based on the C++ language and is synthesized with the Vivado High-Level Synthesis (HLS) tool. The proposed Traffic Manager design supports 40 Gb/s per egress port for 64-byte sized packets, running at 80 MHz when implemented on a ZC706 Xilinx board. A throughput improvement of 4.0× over previous reported works is claimed.
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a high speed Traffic Manager architecture for flow based networking
International New Circuits and Systems Conference, 2017Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:This paper presents a fast Traffic Manager architecture targeting to meet some requirements of the 5G next generation cellular communication technology, and of the high-speed networking devices in the software defined networking context. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G. The proposed Traffic Manager functionalities are policing, scheduling, shaping, and queuing of incoming Traffic (packets) on egress ports in a network processing unit. Policing, scheduling, and shaping guarantee that packets are sent in such a way to meet the allowed bandwidth quotas for each flow, and enforce some desired quality of service. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. A throughput improvement of 2.0× over previous reported works is claimed. The proposed design of the Traffic Manager is capable of providing 15.8 Gbps per egress port for 64 byte sized packets, and it works at 93 MHz when implemented with a Zynq 7000 FPGA from Xilinx.
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a fast systolic priority queue architecture for a flow based Traffic Manager
International New Circuits and Systems Conference, 2016Co-Authors: Imad Benacer, Francoisraymond Boyer, Normand Belanger, Yvon SavariaAbstract:This paper presents a fast systolic priority queue architecture usable in a Traffic Manager. The purpose of the Traffic Manager is to schedule the departure of packets on egress ports in a network processing unit. In the context of this work, this scheduling should ensure that packets are sent in such a way to meet the allowed bandwidth quotas for each packet flow. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G wireless standards. The proposed hardware architecture of the systolic priority queue enables pipelined en/dequeue operations at constant time rate. Detailed description of this processing module is provided, together with the associated algorithm, and the architecture of the Traffic Manager. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. The obtained results are compared across a range of priority queue depths and performance metrics with existing approaches. A throughput improvement of 44% is claimed over best previously reported results. The proposed design of the Traffic Manager works at 118 MHz when implemented on a Kintex-7 FPGA from Xilinx.
Imad Benacer - One of the best experts on this subject based on the ideXlab platform.
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a high speed scalable and programmable Traffic Manager architecture for flow based networking
IEEE Access, 2019Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:In this paper, we present a programmable and scalable Traffic Manager (TM) architecture, targeting requirements of high-speed networking devices, especially in the software-defined networking context. This TM is intended to ease the deployability of new architectures through field-programmable gate array (FPGA) platforms and to make the data plane programmable and scalable. Flow-based networking allows treating Traffic in terms of flows rather than as a simple aggregation of individual packets, which simplifies scheduling and bandwidth allocation for each flow. Programmability brings agility, flexibility, and rapid adaptation to changes, allowing to meet network requirements in real-time. Traffic management with fast queuing and reduced latency plays an important role to support the upcoming 5G cellular communication technology. The proposed TM architecture is coded in C++ and is synthesized with the Vivado High-Level Synthesis tool. This TM is capable of supporting links operating beyond 40 Gb/s, on the ZC706 board and XCVU440-FLGB2377-3-E FPGA device from Xilinx, while achieving 80 Gb/s and 100 Gb/s throughput, respectively. The resulting placed and routed design was tested on the ZC706 board with its embedded ARM processor controlling table updates.
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design of a low latency 40 gb s flow based Traffic Manager using high level synthesis
International Symposium on Circuits and Systems, 2018Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:This paper presents a Traffic Manager architecture targeting to meet today's networking requirements, especially reduced latency, and to support the upcoming 5G technology in the software defined networking context. The proposed Traffic Manager functionalities are policing, scheduling, shaping, and queuing of incoming Traffic (packets). The incoming Traffic is assumed to be a set of flows in a network processing unit. Traffic management imposes constraints on packets to be sent out in such a way to meet the allowed bandwidth quotas for each flow, and enforce desired quality of service (QoS) targets. The FPGA prototyped architecture is based on the C++ language and is synthesized with the Vivado High-Level Synthesis (HLS) tool. The proposed Traffic Manager design supports 40 Gb/s per egress port for 64-byte sized packets, running at 80 MHz when implemented on a ZC706 Xilinx board. A throughput improvement of 4.0× over previous reported works is claimed.
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a high speed Traffic Manager architecture for flow based networking
International New Circuits and Systems Conference, 2017Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:This paper presents a fast Traffic Manager architecture targeting to meet some requirements of the 5G next generation cellular communication technology, and of the high-speed networking devices in the software defined networking context. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G. The proposed Traffic Manager functionalities are policing, scheduling, shaping, and queuing of incoming Traffic (packets) on egress ports in a network processing unit. Policing, scheduling, and shaping guarantee that packets are sent in such a way to meet the allowed bandwidth quotas for each flow, and enforce some desired quality of service. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. A throughput improvement of 2.0× over previous reported works is claimed. The proposed design of the Traffic Manager is capable of providing 15.8 Gbps per egress port for 64 byte sized packets, and it works at 93 MHz when implemented with a Zynq 7000 FPGA from Xilinx.
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a fast systolic priority queue architecture for a flow based Traffic Manager
International New Circuits and Systems Conference, 2016Co-Authors: Imad Benacer, Francoisraymond Boyer, Normand Belanger, Yvon SavariaAbstract:This paper presents a fast systolic priority queue architecture usable in a Traffic Manager. The purpose of the Traffic Manager is to schedule the departure of packets on egress ports in a network processing unit. In the context of this work, this scheduling should ensure that packets are sent in such a way to meet the allowed bandwidth quotas for each packet flow. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G wireless standards. The proposed hardware architecture of the systolic priority queue enables pipelined en/dequeue operations at constant time rate. Detailed description of this processing module is provided, together with the associated algorithm, and the architecture of the Traffic Manager. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. The obtained results are compared across a range of priority queue depths and performance metrics with existing approaches. A throughput improvement of 44% is claimed over best previously reported results. The proposed design of the Traffic Manager works at 118 MHz when implemented on a Kintex-7 FPGA from Xilinx.
Francoisraymond Boyer - One of the best experts on this subject based on the ideXlab platform.
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a high speed scalable and programmable Traffic Manager architecture for flow based networking
IEEE Access, 2019Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:In this paper, we present a programmable and scalable Traffic Manager (TM) architecture, targeting requirements of high-speed networking devices, especially in the software-defined networking context. This TM is intended to ease the deployability of new architectures through field-programmable gate array (FPGA) platforms and to make the data plane programmable and scalable. Flow-based networking allows treating Traffic in terms of flows rather than as a simple aggregation of individual packets, which simplifies scheduling and bandwidth allocation for each flow. Programmability brings agility, flexibility, and rapid adaptation to changes, allowing to meet network requirements in real-time. Traffic management with fast queuing and reduced latency plays an important role to support the upcoming 5G cellular communication technology. The proposed TM architecture is coded in C++ and is synthesized with the Vivado High-Level Synthesis tool. This TM is capable of supporting links operating beyond 40 Gb/s, on the ZC706 board and XCVU440-FLGB2377-3-E FPGA device from Xilinx, while achieving 80 Gb/s and 100 Gb/s throughput, respectively. The resulting placed and routed design was tested on the ZC706 board with its embedded ARM processor controlling table updates.
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design of a low latency 40 gb s flow based Traffic Manager using high level synthesis
International Symposium on Circuits and Systems, 2018Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:This paper presents a Traffic Manager architecture targeting to meet today's networking requirements, especially reduced latency, and to support the upcoming 5G technology in the software defined networking context. The proposed Traffic Manager functionalities are policing, scheduling, shaping, and queuing of incoming Traffic (packets). The incoming Traffic is assumed to be a set of flows in a network processing unit. Traffic management imposes constraints on packets to be sent out in such a way to meet the allowed bandwidth quotas for each flow, and enforce desired quality of service (QoS) targets. The FPGA prototyped architecture is based on the C++ language and is synthesized with the Vivado High-Level Synthesis (HLS) tool. The proposed Traffic Manager design supports 40 Gb/s per egress port for 64-byte sized packets, running at 80 MHz when implemented on a ZC706 Xilinx board. A throughput improvement of 4.0× over previous reported works is claimed.
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a high speed Traffic Manager architecture for flow based networking
International New Circuits and Systems Conference, 2017Co-Authors: Imad Benacer, Francoisraymond Boyer, Yvon SavariaAbstract:This paper presents a fast Traffic Manager architecture targeting to meet some requirements of the 5G next generation cellular communication technology, and of the high-speed networking devices in the software defined networking context. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G. The proposed Traffic Manager functionalities are policing, scheduling, shaping, and queuing of incoming Traffic (packets) on egress ports in a network processing unit. Policing, scheduling, and shaping guarantee that packets are sent in such a way to meet the allowed bandwidth quotas for each flow, and enforce some desired quality of service. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. A throughput improvement of 2.0× over previous reported works is claimed. The proposed design of the Traffic Manager is capable of providing 15.8 Gbps per egress port for 64 byte sized packets, and it works at 93 MHz when implemented with a Zynq 7000 FPGA from Xilinx.
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a fast systolic priority queue architecture for a flow based Traffic Manager
International New Circuits and Systems Conference, 2016Co-Authors: Imad Benacer, Francoisraymond Boyer, Normand Belanger, Yvon SavariaAbstract:This paper presents a fast systolic priority queue architecture usable in a Traffic Manager. The purpose of the Traffic Manager is to schedule the departure of packets on egress ports in a network processing unit. In the context of this work, this scheduling should ensure that packets are sent in such a way to meet the allowed bandwidth quotas for each packet flow. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G wireless standards. The proposed hardware architecture of the systolic priority queue enables pipelined en/dequeue operations at constant time rate. Detailed description of this processing module is provided, together with the associated algorithm, and the architecture of the Traffic Manager. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. The obtained results are compared across a range of priority queue depths and performance metrics with existing approaches. A throughput improvement of 44% is claimed over best previously reported results. The proposed design of the Traffic Manager works at 118 MHz when implemented on a Kintex-7 FPGA from Xilinx.
L I Wenjie - One of the best experts on this subject based on the ideXlab platform.
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research on switching throughput of Traffic Manager in core routers
Frontiers of Electrical and Electronic Engineering in China, 2006Co-Authors: Sun Changhua, Liu Bin, L I WenjieAbstract:A general model is made to analyze switching throughput of Traffic Manager in core routers. By designing a real Traffic Manager that uses the OC-48c interface, the whole system is analyzed and it is pointed out that at least four HSSLs should be employed per CSIX interface when using Vitesse’s GigaStream switch chipset. Meanwhile, at the CSIX interface, the CFrame should be constructed according to the actual size of the last cell of each IP packet. The above principles can guarantee forwarding of IP packets at line rate. A general relationship between throughput and buffering scheme of IP packets in the external memory is given, which is useful in the design of switch fabric in core routers.
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research on switching throughput of Traffic Manager in core routers
Acta Electronica Sinica, 2005Co-Authors: L I WenjieAbstract:We made a general model to analyze switching throughput of Traffic Manager in core routers.By designing a real Traffic Manager which uses the OC-48c interface,we analyze the whole system and point out that at least four HSSLs should be employed per CSIX interface when using Vitesse's GigaStream switch chip set.Meanwhile,at the CSIX interface,the CFrame should be constructed according to the actual size of the last cell of each IP packet.Above principles can guarantee forwarding IP packets at line rate.We give a general relationship between throughput and buffering scheme of IP packets in the external memory,which is useful in the design of switch fabric in core routers.
Stevens Lindsay - One of the best experts on this subject based on the ideXlab platform.
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Evolution of Electronic Approval Request Procedures at Charlotte Douglas International Airport
2018Co-Authors: Stevens Lindsay, Callantine Todd, Staudenmeier RobertAbstract:A departure approval request, or APREQ, establishes a later runway departure time for a flight, allowing it to absorb tactical delay on the ground. APREQ times are traditionally coordinated by a process known as "call-for-release" whereby an airport surface Traffic Manager calls an airspace Traffic Manager on the telephone. This research examines new electronic APREQ coordination enabled by the NASA Airspace Technology Demonstration-2 system and compares it to the traditional call-for-release method of coordination. During the initial deployment period, electronic APREQ coordination was used for more than half of eligible flights. A majority of electronic requests were approved in less than one minute on average. Both the average tactical delay and compliance with the electronically coordinated departure times did not differ significantly from departure times coordinated using call-for-release
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Evolution of Electronic Approval Request Procedures at Charlotte Douglas International Airport
2018Co-Authors: Callantine, Todd J., Staudenmeier Robert, Stevens LindsayAbstract:At many major U.S. airports, a departure approval request, or 'APREQ,' establishes a later runway departure time for a flight, allowing it to absorb tactical delay on the ground. APREQ times are traditionally coordinated by a process known as 'call-for-release' whereby an airport surface Traffic Manager calls an airspace Traffic Manager on the telephone. This research examines new electronic APREQ coordination enabled by the NASA Airspace Technology Demonstration-2 system and compares it to the call-for-release method of coordination. During the initial deployment period, electronic APREQ coordination was used for more than half of eligible flights. A majority of electronic requests were approved in less than one minute on average. Data suggest that both the average tactical delay and compliance with the electronically coordinated departure times did not differ significantly from departure times coordinated using call-for-release
