The Experts below are selected from a list of 4803 Experts worldwide ranked by ideXlab platform
Wen Huang - One of the best experts on this subject based on the ideXlab platform.
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nldd phalo assisted low Trigger scr for high voltage tolerant esd protection without using extra masks
IEEE Electron Device Letters, 2009Co-Authors: Y Shan, J He, B Hu, Wen HuangAbstract:A new silicon-controlled rectifier (SCR) is proposed and realized in the foundry's 0.18-mum CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or Trigger Circuits, the new n-type lightly doped drain and p-type halo-assisted SCR has a Trigger voltage Vt1 as low as 7 V and an ESD robustness exceeding 50 mA/mum, which enables effective ESD protection. Compared with the traditional low-voltage-Triggered SCR, the new structure not only has a lower Trigger voltage but also is more suitable for high-voltage-tolerant applications avoiding any gate-oxide reliability issue.
Y Shan - One of the best experts on this subject based on the ideXlab platform.
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nldd phalo assisted low Trigger scr for high voltage tolerant esd protection without using extra masks
IEEE Electron Device Letters, 2009Co-Authors: Y Shan, J He, B Hu, Wen HuangAbstract:A new silicon-controlled rectifier (SCR) is proposed and realized in the foundry's 0.18-mum CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or Trigger Circuits, the new n-type lightly doped drain and p-type halo-assisted SCR has a Trigger voltage Vt1 as low as 7 V and an ESD robustness exceeding 50 mA/mum, which enables effective ESD protection. Compared with the traditional low-voltage-Triggered SCR, the new structure not only has a lower Trigger voltage but also is more suitable for high-voltage-tolerant applications avoiding any gate-oxide reliability issue.
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pldd nhalo assisted low Trigger scr for high voltage tolerant esd protection in foundry cmos process without extra mask
Electronics Letters, 2009Co-Authors: Y Shan, J He, B HuAbstract:A new semiconductor-controlled rectifier (SCR) is proposed and realised in the foundry 0.18 µm CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or Trigger Circuits, the new p-type lightly-doped-drain and n-type halo (NHALO) assisted SCR has a Trigger voltage as low as 7 V and an ESD robustness exceeding 50 mA/µm to provide an effective protection. Compared with traditional LVTSCR, the new structure not only has a lower Trigger voltage, but can also be more suitable for high-voltage tolerant applications without the gate-oxide reliability issue.
B Hu - One of the best experts on this subject based on the ideXlab platform.
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nldd phalo assisted low Trigger scr for high voltage tolerant esd protection without using extra masks
IEEE Electron Device Letters, 2009Co-Authors: Y Shan, J He, B Hu, Wen HuangAbstract:A new silicon-controlled rectifier (SCR) is proposed and realized in the foundry's 0.18-mum CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or Trigger Circuits, the new n-type lightly doped drain and p-type halo-assisted SCR has a Trigger voltage Vt1 as low as 7 V and an ESD robustness exceeding 50 mA/mum, which enables effective ESD protection. Compared with the traditional low-voltage-Triggered SCR, the new structure not only has a lower Trigger voltage but also is more suitable for high-voltage-tolerant applications avoiding any gate-oxide reliability issue.
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pldd nhalo assisted low Trigger scr for high voltage tolerant esd protection in foundry cmos process without extra mask
Electronics Letters, 2009Co-Authors: Y Shan, J He, B HuAbstract:A new semiconductor-controlled rectifier (SCR) is proposed and realised in the foundry 0.18 µm CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or Trigger Circuits, the new p-type lightly-doped-drain and n-type halo (NHALO) assisted SCR has a Trigger voltage as low as 7 V and an ESD robustness exceeding 50 mA/µm to provide an effective protection. Compared with traditional LVTSCR, the new structure not only has a lower Trigger voltage, but can also be more suitable for high-voltage tolerant applications without the gate-oxide reliability issue.
J He - One of the best experts on this subject based on the ideXlab platform.
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nldd phalo assisted low Trigger scr for high voltage tolerant esd protection without using extra masks
IEEE Electron Device Letters, 2009Co-Authors: Y Shan, J He, B Hu, Wen HuangAbstract:A new silicon-controlled rectifier (SCR) is proposed and realized in the foundry's 0.18-mum CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or Trigger Circuits, the new n-type lightly doped drain and p-type halo-assisted SCR has a Trigger voltage Vt1 as low as 7 V and an ESD robustness exceeding 50 mA/mum, which enables effective ESD protection. Compared with the traditional low-voltage-Triggered SCR, the new structure not only has a lower Trigger voltage but also is more suitable for high-voltage-tolerant applications avoiding any gate-oxide reliability issue.
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pldd nhalo assisted low Trigger scr for high voltage tolerant esd protection in foundry cmos process without extra mask
Electronics Letters, 2009Co-Authors: Y Shan, J He, B HuAbstract:A new semiconductor-controlled rectifier (SCR) is proposed and realised in the foundry 0.18 µm CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or Trigger Circuits, the new p-type lightly-doped-drain and n-type halo (NHALO) assisted SCR has a Trigger voltage as low as 7 V and an ESD robustness exceeding 50 mA/µm to provide an effective protection. Compared with traditional LVTSCR, the new structure not only has a lower Trigger voltage, but can also be more suitable for high-voltage tolerant applications without the gate-oxide reliability issue.
Ching-te Chuang - One of the best experts on this subject based on the ideXlab platform.
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Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt Trigger Circuits
IEEE Transactions on Circuits and Systems II: Express Briefs, 2004Co-Authors: J.b. Kuang, Ching-te ChuangAbstract:This paper presents a new circuit technique to alleviate the uncontrollable floating-body-induced hysteretic component present in the transfer characteristics of voltage-mode CMOS Schmitt Trigger Circuits in a partially depleted silicon-on-insulator technology. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme, resulting in improved noise immunity and well-defined hysteresis behavior for the Schmitt Trigger circuit that is suitable for use as a low-noise receiver, level shifter, waveform-reshaping circuit, and delay element in very large-scale integrated applications.
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pd soi cmos schmitt Trigger Circuits with controllable hysteresis
International Symposium on VLSI Technology Systems and Applications, 2001Co-Authors: J.b. Kuang, Ching-te ChuangAbstract:This paper presents an SOI circuit technique, which eliminates the uncontrollable floating-body-induce hysteretic component in the transfer characteristics of CMOS Schmitt Triggers. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme. The resulting design possesses improved noise immunity and well-defined hysteresis behavior, suitable for use as a low-noise receiver, waveform-reshaping circuit, or delay element in VLSI applications.
