The Experts below are selected from a list of 9 Experts worldwide ranked by ideXlab platform
G M Blair - One of the best experts on this subject based on the ideXlab platform.
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the equivalence of Twos Complement addition and the conversion of redundant binary to Twos Complement Numbers
IEEE transactions on circuits and systems. 2 Analog and digital signal processing, 1998Co-Authors: G M BlairAbstract:The equivalence between redundant-binary (RB) to Twos-Complement Number conversion and Twos-Complement addition is shown using a simple transform between the two Number domains. As a consequence, all hardware architectures designed for either operation may be easily adapted to implement the other.
Aachen D Germany - One of the best experts on this subject based on the ideXlab platform.
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LOGIC SYNTHESIS OF BINARY CARRYSAVE AND MIXEDRADIX ARITHMETIC FOR DIGITAL SIGNAL PROCESSING
2016Co-Authors: Iss Templergraben, Aachen D GermanyAbstract:email bitterliertrwthaachende Abstract All the commercially available logicsynthesis tools cur rently use only nonredundant binary and Twos Complement Number representations for representing the results of arithmetic operators In this paper we analyze and compare silicon realestate and throughput of wordparallel arithmetic circuits add and shift type arithmetics based on various redundant Number representations and compare these results with the automatically optimized Twos Complement implementations The literature on redundant Number representations typically recommends radix arithmetics for fullcustom or a traditional semicustom design style We show that the radix implementation is often not optimal for a logicsynthesis based semicustom design style Instead a highradix or a mixedradix implementation which we derive in this paper should be considere
Earl E Swartzlander - One of the best experts on this subject based on the ideXlab platform.
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efficient sign extension for multiple addition
Proceedings of SPIE - The International Society for Optical Engineering, 2003Co-Authors: Robert T Grisamore, Earl E SwartzlanderAbstract:A technique for reducing the sign extension overhead in adder trees is presented. A generalized version of the technique is shown to reduce the Number of redundant sign extension computations required for reducing parallel adder trees from N terms to two terms. Additionally, the technique eliminates the fan-out latency that traditional sign extension places on late arriving sign bits. Twos Complement Number growth is also managed in carry-save form without the need for carry propagation. The application of the technique to 2N term adder trees is demonstrated. The implementation requires no computational overhead and needs minimal hardware. This design not only reduces hardware complexity, but also reduces computation delay. Finally, a simple circuit transformation to the traditional 4-2 compressor allows simple construction of circuits utilizing the technique.
Iss Templergraben - One of the best experts on this subject based on the ideXlab platform.
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LOGIC SYNTHESIS OF BINARY CARRYSAVE AND MIXEDRADIX ARITHMETIC FOR DIGITAL SIGNAL PROCESSING
2016Co-Authors: Iss Templergraben, Aachen D GermanyAbstract:email bitterliertrwthaachende Abstract All the commercially available logicsynthesis tools cur rently use only nonredundant binary and Twos Complement Number representations for representing the results of arithmetic operators In this paper we analyze and compare silicon realestate and throughput of wordparallel arithmetic circuits add and shift type arithmetics based on various redundant Number representations and compare these results with the automatically optimized Twos Complement implementations The literature on redundant Number representations typically recommends radix arithmetics for fullcustom or a traditional semicustom design style We show that the radix implementation is often not optimal for a logicsynthesis based semicustom design style Instead a highradix or a mixedradix implementation which we derive in this paper should be considere
Robert T Grisamore - One of the best experts on this subject based on the ideXlab platform.
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efficient sign extension for multiple addition
Proceedings of SPIE - The International Society for Optical Engineering, 2003Co-Authors: Robert T Grisamore, Earl E SwartzlanderAbstract:A technique for reducing the sign extension overhead in adder trees is presented. A generalized version of the technique is shown to reduce the Number of redundant sign extension computations required for reducing parallel adder trees from N terms to two terms. Additionally, the technique eliminates the fan-out latency that traditional sign extension places on late arriving sign bits. Twos Complement Number growth is also managed in carry-save form without the need for carry propagation. The application of the technique to 2N term adder trees is demonstrated. The implementation requires no computational overhead and needs minimal hardware. This design not only reduces hardware complexity, but also reduces computation delay. Finally, a simple circuit transformation to the traditional 4-2 compressor allows simple construction of circuits utilizing the technique.
