The Experts below are selected from a list of 213 Experts worldwide ranked by ideXlab platform
Zhongqun Tian - One of the best experts on this subject based on the ideXlab platform.
-
confined chemical etching for electrochemical machining with nanoscale accuracy
Accounts of Chemical Research, 2016Co-Authors: Dongping Zhan, Lianhuan Han, Jie Zhang, Kang Shi, Jianzhang Zhou, Zhaowu Tian, Zhongqun TianAbstract:ConspectusIn the past several decades, electrochemical machining (ECM) has enjoyed the reputation of a powerful technique in the manufacturing industry. Conventional ECM methods can be classified as electrolytic machining and electroforming: the former is based on anodic dissolution and the latter is based on cathodic deposition of metallic materials. Strikingly, ECM possesses several advantages over mechanical machining, such as high removal rate, the capability of making complex three-dimensional structures, and the practicability for difficult-to-cut materials. Additionally, ECM avoids tool wear and thermal or mechanical stress on machining surfaces. Thus, ECM is widely used for various industrial applications in the fields of aerospace, automobiles, electronics, etc.Nowadays, miniaturization and integration of functional components are becoming significant in ultralarge scale integration (ULSI) Circuits, microelectromechanical systems (MEMS), and miniaturized total analysis systems (μ-TAS). As predict...
-
confined chemical etching for electrochemical machining with nanoscale accuracy
Accounts of Chemical Research, 2016Co-Authors: Dongping Zhan, Jie Zhang, Jianzhang Zhou, Zhaowu Tian, Zhongqun TianAbstract:ConspectusIn the past several decades, electrochemical machining (ECM) has enjoyed the reputation of a powerful technique in the manufacturing industry. Conventional ECM methods can be classified as electrolytic machining and electroforming: the former is based on anodic dissolution and the latter is based on cathodic deposition of metallic materials. Strikingly, ECM possesses several advantages over mechanical machining, such as high removal rate, the capability of making complex three-dimensional structures, and the practicability for difficult-to-cut materials. Additionally, ECM avoids tool wear and thermal or mechanical stress on machining surfaces. Thus, ECM is widely used for various industrial applications in the fields of aerospace, automobiles, electronics, etc.Nowadays, miniaturization and integration of functional components are becoming significant in ultralarge scale integration (ULSI) Circuits, microelectromechanical systems (MEMS), and miniaturized total analysis systems (μ-TAS). As predict...
Eby G Friedman - One of the best experts on this subject based on the ideXlab platform.
-
Estimation of On-Chip Simultaneous Switching Noise in VDSM CMOS Circuits
2007Co-Authors: K T Tang, Eby G FriedmanAbstract:On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI Circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped model. The waveform describing the SSN voltage is quite close to the waveform obtained from SPICE. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations. I. INTRODUCTION The trend of next generation integrated circuit (IC) technology is towards higher speeds and densities. The total capacitive load associated with the internal circuitry is increasing in both current and next generation VLSI Circuits [1], [2]. As the operating frequency increases, the average on-chip current required to charge (and discharge) these capacitances also increases, while the time during which the current being switched decreases. Therefore, a large change ..
-
simultaneous switching noise in on chip cmos power distribution networks
IEEE Transactions on Very Large Scale Integration Systems, 2002Co-Authors: K T Tang, Eby G FriedmanAbstract:Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) Circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.
-
on chip spl delta i noise in the power distribution networks of high speed cmos integrated Circuits
International Conference on ASIC, 2000Co-Authors: K T Tang, Eby G FriedmanAbstract:On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI Circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped RLC model. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak simultaneous switching noise voltage on the circuit behavior.
Dongping Zhan - One of the best experts on this subject based on the ideXlab platform.
-
confined chemical etching for electrochemical machining with nanoscale accuracy
Accounts of Chemical Research, 2016Co-Authors: Dongping Zhan, Lianhuan Han, Jie Zhang, Kang Shi, Jianzhang Zhou, Zhaowu Tian, Zhongqun TianAbstract:ConspectusIn the past several decades, electrochemical machining (ECM) has enjoyed the reputation of a powerful technique in the manufacturing industry. Conventional ECM methods can be classified as electrolytic machining and electroforming: the former is based on anodic dissolution and the latter is based on cathodic deposition of metallic materials. Strikingly, ECM possesses several advantages over mechanical machining, such as high removal rate, the capability of making complex three-dimensional structures, and the practicability for difficult-to-cut materials. Additionally, ECM avoids tool wear and thermal or mechanical stress on machining surfaces. Thus, ECM is widely used for various industrial applications in the fields of aerospace, automobiles, electronics, etc.Nowadays, miniaturization and integration of functional components are becoming significant in ultralarge scale integration (ULSI) Circuits, microelectromechanical systems (MEMS), and miniaturized total analysis systems (μ-TAS). As predict...
-
confined chemical etching for electrochemical machining with nanoscale accuracy
Accounts of Chemical Research, 2016Co-Authors: Dongping Zhan, Jie Zhang, Jianzhang Zhou, Zhaowu Tian, Zhongqun TianAbstract:ConspectusIn the past several decades, electrochemical machining (ECM) has enjoyed the reputation of a powerful technique in the manufacturing industry. Conventional ECM methods can be classified as electrolytic machining and electroforming: the former is based on anodic dissolution and the latter is based on cathodic deposition of metallic materials. Strikingly, ECM possesses several advantages over mechanical machining, such as high removal rate, the capability of making complex three-dimensional structures, and the practicability for difficult-to-cut materials. Additionally, ECM avoids tool wear and thermal or mechanical stress on machining surfaces. Thus, ECM is widely used for various industrial applications in the fields of aerospace, automobiles, electronics, etc.Nowadays, miniaturization and integration of functional components are becoming significant in ultralarge scale integration (ULSI) Circuits, microelectromechanical systems (MEMS), and miniaturized total analysis systems (μ-TAS). As predict...
Hannu Tenhunen - One of the best experts on this subject based on the ideXlab platform.
-
Fast modeling of core switching noise on distributed LRC power grid in ULSI Circuits
IEEE Transactions on Advanced Packaging, 2001Co-Authors: L R Zheng, Hannu TenhunenAbstract:As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark Circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0/spl plusmn/5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) Circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted.
-
Fast modeling of core switching noise on distributed LRC power grid in ULSI Circuits
IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524), 2000Co-Authors: L R Zheng, Hannu TenhunenAbstract:A sophisticated on-chip power grid model consisting of distributed LRC elements is proposed for on-chip power distribution analysis. Fast equations for peak noise estimations are formulated. Noise distribution on a power grid with any topology is efficiently and accurately computed. HSPICE simulations confirmed its efficiency and accuracy. The model is suitable for both early stage analysis and post-layout verifications in on-chip power distribution design. Global and local optimization such as buffer sizing, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted.
K T Tang - One of the best experts on this subject based on the ideXlab platform.
-
Estimation of On-Chip Simultaneous Switching Noise in VDSM CMOS Circuits
2007Co-Authors: K T Tang, Eby G FriedmanAbstract:On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI Circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped model. The waveform describing the SSN voltage is quite close to the waveform obtained from SPICE. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations. I. INTRODUCTION The trend of next generation integrated circuit (IC) technology is towards higher speeds and densities. The total capacitive load associated with the internal circuitry is increasing in both current and next generation VLSI Circuits [1], [2]. As the operating frequency increases, the average on-chip current required to charge (and discharge) these capacitances also increases, while the time during which the current being switched decreases. Therefore, a large change ..
-
simultaneous switching noise in on chip cmos power distribution networks
IEEE Transactions on Very Large Scale Integration Systems, 2002Co-Authors: K T Tang, Eby G FriedmanAbstract:Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) Circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.
-
on chip spl delta i noise in the power distribution networks of high speed cmos integrated Circuits
International Conference on ASIC, 2000Co-Authors: K T Tang, Eby G FriedmanAbstract:On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI Circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped RLC model. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak simultaneous switching noise voltage on the circuit behavior.
