The Experts below are selected from a list of 41100 Experts worldwide ranked by ideXlab platform
Wei Jiang - One of the best experts on this subject based on the ideXlab platform.
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Platform based resource binding using a distributed register file microarchitecture
International Conference on Computer Aided Design, 2006Co-Authors: Jason Cong, Yiping Fan, Wei JiangAbstract:Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the Underlying Platform features. This paper presents a Platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA Platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.
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Platform based resource binding using a distributed register file microarchitecture
International Conference on Computer Aided Design, 2006Co-Authors: Jason Cong, Yiping Fan, Wei JiangAbstract:Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the Underlying Platform features. This paper presents a Platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA Platform, our experimental results show a 2times logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach
Jason Cong - One of the best experts on this subject based on the ideXlab platform.
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simultaneous resource binding and interconnection optimization based on a distributed register file microarchitecture
ACM Transactions on Design Automation of Electronic Systems, 2009Co-Authors: Jason Cong, Yiping FanAbstract:Behavior synthesis and optimization beyond the register-transfer level require an efficient utilization of the Underlying Platform features. This article presents a Platform-based resource binding approach based on a Distributed Register-File Microarchitecture (DRFM), which makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. DRFM contains multiple islands, each having a local register file, a functional unit pool, and data-routing logic. Compared to the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in a substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Given the scheduling solution and resource (functional units) constraints, two novel algorithms in the resource binding stage are developed based on DRFM: (i) a simultaneous DRFM clustering and binding algorithm, which decides the configuration of DRFM and the assignment of operations into islands with the focus on optimizing global connections; (ii) a data-forwarding scheduling algorithm, which takes advantage of the operation slacks to handle the read-port restriction of register files. On the Xilinx Virtex4 FPGA Platform, experimental results with a set of real-life test cases show a 50p logic area reduction achieved by applying our approach, with a 14.6p performance improvement, compared to the traditional discrete-register-based approach. Also, experiments on small-size designs show that our algorithm produces the same number of total connections and at most one more maximum feeding-in connection compared to optimal solutions generated by ILP.
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Platform based resource binding using a distributed register file microarchitecture
International Conference on Computer Aided Design, 2006Co-Authors: Jason Cong, Yiping Fan, Wei JiangAbstract:Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the Underlying Platform features. This paper presents a Platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA Platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.
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Platform based resource binding using a distributed register file microarchitecture
International Conference on Computer Aided Design, 2006Co-Authors: Jason Cong, Yiping Fan, Wei JiangAbstract:Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the Underlying Platform features. This paper presents a Platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA Platform, our experimental results show a 2times logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach
Yiping Fan - One of the best experts on this subject based on the ideXlab platform.
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simultaneous resource binding and interconnection optimization based on a distributed register file microarchitecture
ACM Transactions on Design Automation of Electronic Systems, 2009Co-Authors: Jason Cong, Yiping FanAbstract:Behavior synthesis and optimization beyond the register-transfer level require an efficient utilization of the Underlying Platform features. This article presents a Platform-based resource binding approach based on a Distributed Register-File Microarchitecture (DRFM), which makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. DRFM contains multiple islands, each having a local register file, a functional unit pool, and data-routing logic. Compared to the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in a substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Given the scheduling solution and resource (functional units) constraints, two novel algorithms in the resource binding stage are developed based on DRFM: (i) a simultaneous DRFM clustering and binding algorithm, which decides the configuration of DRFM and the assignment of operations into islands with the focus on optimizing global connections; (ii) a data-forwarding scheduling algorithm, which takes advantage of the operation slacks to handle the read-port restriction of register files. On the Xilinx Virtex4 FPGA Platform, experimental results with a set of real-life test cases show a 50p logic area reduction achieved by applying our approach, with a 14.6p performance improvement, compared to the traditional discrete-register-based approach. Also, experiments on small-size designs show that our algorithm produces the same number of total connections and at most one more maximum feeding-in connection compared to optimal solutions generated by ILP.
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Platform based resource binding using a distributed register file microarchitecture
International Conference on Computer Aided Design, 2006Co-Authors: Jason Cong, Yiping Fan, Wei JiangAbstract:Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the Underlying Platform features. This paper presents a Platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA Platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.
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Platform based resource binding using a distributed register file microarchitecture
International Conference on Computer Aided Design, 2006Co-Authors: Jason Cong, Yiping Fan, Wei JiangAbstract:Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the Underlying Platform features. This paper presents a Platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the Platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA Platform, our experimental results show a 2times logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach
Bernhard Rinner - One of the best experts on this subject based on the ideXlab platform.
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trustcam security and privacy protection for an embedded smart camera based on trusted computing
Advanced Video and Signal Based Surveillance, 2010Co-Authors: Thomas Winkler, Bernhard RinnerAbstract:Security and privacy protection are critical issues forpublic acceptance of camera networks. Smart cameras,with onboard image processing, can be used to identifyand remove privacy sensitive image regions. Existing approaches,however, only address isolated aspects withoutconsidering the integration with established security technologiesand the Underlying Platform. This work tries to fillthis gap and presents TrustCAM, a security-enhanced smartcamera. Based on Trusted Computing, we realize integrityprotection, authenticity and confidentiality of image data.Multiple levels of privacy protection, together with accesscontrol, are supported. Impact on overall system performanceis evaluated on a real prototype implementation.
Farinaz Koushanfar - One of the best experts on this subject based on the ideXlab platform.
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perform ml performance optimized machine learning by Platform and content aware customization
Design Automation Conference, 2016Co-Authors: Azalia Mirhoseini, Ebrahim M Songhori, Bita Darvish Rouhani, Farinaz KoushanfarAbstract:We propose Perform-ML, the first Machine Learning (ML) framework for analysis of massive and dense data which customizes the algorithm to the Underlying Platform for the purpose of achieving optimized resource efficiency. Perform-ML creates a performance model quantifying the computational cost of iterative analysis algorithms on a pertinent Platform in terms of FLOPs, communication, and memory, which characterize runtime, storage, and energy. The core of Perform-ML is a novel parametric data projection algorithm, called Elastic Dictionary (ExD), that enables versatile and sparse representations of the data which can help in minimizing performance cost. We show that Perform-ML can achieve the optimal performance objective, according to our cost model, by Platform aware tuning of the ExD parameters. An accompanying API ensures automated applicability of Perform-ML to various algorithms, datasets, and Platforms. Proof-of-concept evaluations of massive and dense data on different Platforms demonstrate more than an order of magnitude improvements in performance compared to the state of the art, within guaranteed user-defined error bounds.
