The Experts below are selected from a list of 405 Experts worldwide ranked by ideXlab platform
Rodolfo, Taciano Ares - One of the best experts on this subject based on the ideXlab platform.
-
Uma exploração do espaço de projeto de processadores com hardware de ponto flutuante em FPGAS
Pontifícia Universidade Católica do Rio Grande do Sul, 2010Co-Authors: Rodolfo, Taciano AresAbstract:Circuitos aritméticos são parte fundamental de sistemas digitais, uma vez que cada porção de informação processada por estes deve ter sido codificada previamente sob a forma de números, e que a aritmética é a forma por excelência de proceder à manipulação sistemática de números. Existe uma grande quantidade de esquemas de codificação usados em sistemas digitais, mas três formas de representação se sobressaem por serem usadas na maioria maciça das situações: números sem sinal, números inteiros e a representação de ponto flutuante. Os dois primeiros são mais simples e mais universais, mas algumas aplicações exigem o recurso à faixa estendida de valores e à precisão incrementada de representações de ponto flutuante. Embora o uso de hardware de ponto flutuante em FPGAs tenha sido por muito tempo considerado inviável ou relegado ao uso apenas em dispositivos e plataformas de alto custo, esta não é mais a situação atual.Este trabalho descreve o processo de projeto, a implementação física e uma avaliação preliminar de unidades de processamento de ponto flutuante de precisão simples em hardware para uma arquitetura de processador MIPS. Exploram-se várias implementações completas que têm a forma de coprocessadores fortemente acoplados. Estes coprocessadores ocupam apenas 4% de um FPGA de tamanho médio, enquanto o processador em si ocupa 3% do mesmo dispositivo. O processo de exploração do espaço de soluções de projeto descrito aqui considera as figuras de mérito área, desempenho e potência e considera variações na escolha da ferramenta de síntese, do método de geração a unidade de ponto flutuante e questões arquiteturais tais como estratégias de uso de relógios. Os experimentos conduzidos mostram reduções de mais de 20 vezes na contagem do número de ciclos de relógio do processador, para módulos de aplicação típicos que usam ponto flutuante de forma intensiva, quando comparado com processamento de representações de ponto flutuante emulado em software.Arithmetic circuits are a fundamental part of digital systems, since every piece of information processed by them must first be encoded as numbers, and arithmetic is the ultimate way to systematically manipulate numbers. There exists a large number of available number encoding schemes, but three of these stand as useful in most situations: Unsigned, Integer and floating point. The first two are simpler and more universal, but some applications do require the recourse to the extended range of values, and the increased precision of floating point representations. Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case.This work describes the design process, the implementation and a preliminary evaluation of single-precision floating point hardware units for an instance of the MIPS processor architecture. It explores several fully-fledged implementations that have the form of strongly coupled coprocessors. These coprocessors take as little room as 4% of a medium-sized FPGA, while the processor CPU may take only 3% of the same device. The space exploration process described here values area, performance and power metrics and considers variations on the choice of synthesis tool, floating point unit generation method and architectural issues such as clocking schemes. The conducted experiments show reductions of more than 20 times in clock cycles count for typical floating point application modules, when compared to the use of software-emulated floating point processing
-
Uma explora??o do espa?o de projeto de processadores com hardware de ponto flutuante em FPGAS
Faculdade de Inform?ca, 2010Co-Authors: Rodolfo, Taciano AresAbstract:Made available in DSpace on 2015-04-14T14:49:59Z (GMT). No. of bitstreams: 1 447663.pdf: 3152066 bytes, checksum: ada0593d3cfeecc7c99152d88798658e (MD5) Previous issue date: 2010-03-15Arithmetic circuits are a fundamental part of digital systems, since every piece of information processed by them must first be encoded as numbers, and arithmetic is the ultimate way to systematically manipulate numbers. There exists a large number of available number encoding schemes, but three of these stand as useful in most situations: Unsigned, Integer and floating point. The first two are simpler and more universal, but some applications do require the recourse to the extended range of values, and the increased precision of floating point representations. Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case. This work describes the design process, the implementation and a preliminary evaluation of single-precision floating point hardware units for an instance of the MIPS processor architecture. It explores several fully-fledged implementations that have the form of strongly coupled coprocessors. These coprocessors take as little room as 4% of a medium-sized FPGA, while the processor CPU may take only 3% of the same device. The space exploration process described here values area, performance and power metrics and considers variations on the choice of synthesis tool, floating point unit generation method and architectural issues such as clocking schemes. The conducted experiments show reductions of more than 20 times in clock cycles count for typical floating point application modules, when compared to the use of software-emulated floating point processing.Circuitos aritm?ticos s?o parte fundamental de sistemas digitais, uma vez que cada por??o de informa??o processada por estes deve ter sido codificada previamente sob a forma de n?meros, e que a aritm?tica ? a forma por excel?ncia de proceder ? manipula??o sistem?tica de n?meros. Existe uma grande quantidade de esquemas de codifica??o usados em sistemas digitais, mas tr?s formas de representa??o se sobressaem por serem usadas na maioria maci?a das situa??es: n?meros sem sinal, n?meros inteiros e a representa??o de ponto flutuante. Os dois primeiros s?o mais simples e mais universais, mas algumas aplica??es exigem o recurso ? faixa estendida de valores e ? precis?o incrementada de representa??es de ponto flutuante. Embora o uso de hardware de ponto flutuante em FPGAs tenha sido por muito tempo considerado invi?vel ou relegado ao uso apenas em dispositivos e plataformas de alto custo, esta n?o ? mais a situa??o atual. Este trabalho descreve o processo de projeto, a implementa??o f?sica e uma avalia??o preliminar de unidades de processamento de ponto flutuante de precis?o simples em hardware para uma arquitetura de processador MIPS. Exploram-se v?rias implementa??es completas que t?m a forma de coprocessadores fortemente acoplados. Estes coprocessadores ocupam apenas 4% de um FPGA de tamanho m?dio, enquanto o processador em si ocupa 3% do mesmo dispositivo. O processo de explora??o do espa?o de solu??es de projeto descrito aqui considera as figuras de m?rito ?rea, desempenho e pot?ncia e considera varia??es na escolha da ferramenta de s?ntese, do m?todo de gera??o a unidade de ponto flutuante e quest?es arquiteturais tais como estrat?gias de uso de rel?gios. Os experimentos conduzidos mostram redu??es de mais de 20 vezes na contagem do n?mero de ciclos de rel?gio do processador, para m?dulos de aplica??o t?picos que usam ponto flutuante de forma intensiva, quando comparado com processamento de representa??es de ponto flutuante emulado em software
Hamilton Stuart - One of the best experts on this subject based on the ideXlab platform.
-
Landsat 8 Color-IR mosaic, TIFF, Lake Victoria Wateshed, Raster, 2016
Harvard Dataverse, 2024Co-Authors: Hamilton StuartAbstract:Zip Files Can be Downloaded From: https://drive.google.com/drive/folders/0B0A7-n4PmIvhRFNieGV6ekZtaWM Natural Color TIFF, Lake Victoria, Raster, 2016 Reference Information and Units: Spatial Reference: WGS_1984_UTM_zone_37N Geographic Datum: D_WGS_1984 Cell Size: 30, 30 (meter) Bands: 3 NoData Value: 0, 0, 0 Pixel Type: Unsigned Integer Pixel Depth: 16 Bit Pyramids: level: 7, resampling: Nearest Neighbor File Naming Convention: ColorInfrared_Mosaic.TIF Data Origin: The original scenes were Landsat 8 data that were downloaded from the USGS. Scenes were picked that were from 2016 and had a cloud cover percentage less than 10%. One Scene was used from 2015 due to no suitable scenes being available for 2016. Data Development: This TIFF image was created using ArcGIS. To create the color infrared composite each individual scene needs have the red, green, and near infrared bands together. Using Landsat 8 data means that near infrared is band 5, red is band 4, and green is band 3. When setting up the individual scene composites the no data value is set to 0. This gets ride of the black square that surrounds the TIF. Finally when the individual scenes are completed they are ready to be mosaicked. The final mosaic used a blend mosaic type. The blend type decides the output cell based on a horizontally weighted calculation of the values from the overlapping cells. This method helps clean up the output image. When the final mosaic is complete the last step was to create pyramids and calculate statistics
-
Landsat 8 Natural Color mosaic, TIFF, Lake Victoria Wateshed, Raster, 2016
Harvard Dataverse, 2024Co-Authors: Hamilton StuartAbstract:Zip Files Can be Downloaded From: https://drive.google.com/drive/folders/0B0A7-n4PmIvhRFNieGV6ekZtaWM Natural Color TIFF, Lake Victoria, Raster, 2016 Reference Information and Units: Spatial Reference: WGS_1984_UTM_zone_37N Geographic Datum: D_WGS_1984 Cell Size: 30, 30 (meter) Bands: 3 NoData Value: 0, 0, 0 Pixel Type: Unsigned Integer Pixel Depth: 16 Bit Pyramids: level: 7, resampling: Nearest Neighbor File Naming Convention: NaturalColor_Mosaic.TIF Data Origin: The original scenes were Landsat 8 data that were downloaded from the USGS. Scenes were picked that were from 2016 and had a cloud cover percentage less than 10%. One Scene was used from 2015 due to no suitable scenes being available for 2016. Data Development: This TIFF image was created using ArcGIS. To create the natural color composite each individual scene needs have the red, green, and blue bands together. Using Landsat 8 data means that red is band 4, green is band 3, and blue is band 2. When setting up the individual scene composites the no data value is set to 0. This gets ride of the black square that surrounds the TIF. Finally when the individual scenes are completed they are ready to be mosaicked. The final mosaic used a blend mosaic type. The blend type decides the output cell based on a horizontally weighted calculation of the values from the overlapping cells. This method helps clean up the output image. When the final mosaic is complete the last step was to create pyramids and calculate statistics
Rasim Latifovic - One of the best experts on this subject based on the ideXlab platform.
-
radiometric normalization compositing and quality control for satellite high resolution image mosaics over large areas
IEEE Transactions on Geoscience and Remote Sensing, 2001Co-Authors: Josef Cihlar, J Beaubien, Rasim LatifovicAbstract:An objective normalization procedure has been developed to create image mosaics of radiometric equalization radiometric normalization for image mosaics (RNIM). The procedure employs a band-specific principal component analysis for overlap areas to achieve accurate and consistent radiometric transforms in each spectral band. It is demonstrated that the result of radiometric equalization is independent of the order of images to be mosaicked after the radiometric normalization adjustment is made. The selection of corresponding pixel pairs in the overlap area is controlled by using band-specific linear correlation coefficients, and the criteria for rejecting the cloudy and land-cover changed pixels. The final result is controlled quantitatively by employing the first and second principal components for the input data, which in turn depend on the selection of corresponding pixel pairs in the overlap area. In general, the radiometric resolution of input images can be conserved as long as gain /spl ges/1 and offset /spl ges/0 because of the stored format of the Unsigned Integer. The RNIM procedure accommodates these conditions. To take the best advantage of the data in the overlap areas, a pixel-based composite technique is employed in the production of the final mosaic. The selection of corresponding pixel pairs and the final result can be controlled and assessed with quantitative criteria. Therefore, this approach produces an objective, analyst-independent result and can be automated. The method has been successfully applied to six Landsat TM images of the BOREAS transect in Saskatchewan and Manitoba, Canada.
David Gregg - One of the best experts on this subject based on the ideXlab platform.
-
Scalar Arithmetic Multiple Data: Customizable Precision for Deep Neural Networks
2019 IEEE 26th Symposium on Computer Arithmetic (ARITH), 2019Co-Authors: Andrew Anderson, Michael Doyle, David GreggAbstract:Quantization of weights and activations in Deep Neural Networks (DNNs) is a powerful technique for network compression, and has enjoyed significant attention and success. However, much of the inference-time benefit of quantization is accessible only through customized hardware accelerators or with an FPGA implementation of quantized arithmetic. Building on prior work, we show how to construct very fast implementations of arbitrary bit-precise signed and Unsigned Integer operations using a software technique which logically embeds a vector architecture with custom bit-width lanes in fixed-width scalar arithmetic. At the strongest level of quantization, our approach yields a maximum speedup of ~ 6× on an x86 platform, and ~ 10× on an ARM platform versus quantization to native 8-bit Integers.
Gregg David - One of the best experts on this subject based on the ideXlab platform.
-
Scalar Arithmetic Multiple Data: Customizable Precision for Deep Neural Networks
'Institute of Electrical and Electronics Engineers (IEEE)', 2019Co-Authors: Anderson Andrew, Gregg DavidAbstract:Quantization of weights and activations in Deep Neural Networks (DNNs) is a powerful technique for network compression, and has enjoyed significant attention and success. However, much of the inference-time benefit of quantization is accessible only through the use of customized hardware accelerators or by providing an FPGA implementation of quantized arithmetic. Building on prior work, we show how to construct arbitrary bit-precise signed and Unsigned Integer operations using a software technique which logically \emph{embeds} a vector architecture with custom bit-width lanes in universally available fixed-width scalar arithmetic. We evaluate our approach on a high-end Intel Haswell processor, and an embedded ARM processor. Our approach yields very fast implementations of bit-precise custom DNN operations, which often match or exceed the performance of operations quantized to the sizes supported in native arithmetic. At the strongest level of quantization, our approach yields a maximum speedup of $\thicksim6\times$ on the Intel platform, and $\thicksim10\times$ on the ARM platform versus quantization to native 8-bit Integers
