The Experts below are selected from a list of 9432 Experts worldwide ranked by ideXlab platform

Po-hung Chen - One of the best experts on this subject based on the ideXlab platform.

  • a risc v Vector Processor with simultaneous switching switched capacitor dc dc converters in 28 nm fdsoi
    IEEE Journal of Solid-state Circuits, 2016
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Milovan Blagojevic, Pi-feng Chiu, Steven Bailey, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

  • A RISC-V Vector Processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
    2015 Symposium on VLSI Circuits (VLSI Circuits), 2015
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-feng Chiu, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

Guy G.f. Lemieux - One of the best experts on this subject based on the ideXlab platform.

  • venice a compact Vector Processor for fpga applications
    Field-Programmable Custom Computing Machines, 2012
    Co-Authors: Aaron Severance, Guy G.f. Lemieux
    Abstract:

    VENICE is a new soft Vector Processor (SVP) for FPGA applications that is designed for maximum through-put with a small number (1 to 4) of ALUs. By increasing clock speed and eliminating bottlenecks in ALU utilization, VENICE achieves over 2x better performance-per-logic block than VEGAS, the previous best SVP. VENICE is also simpler to program, as its instructions use standard C pointers into a scratchpad memory rather than Vector registers.

  • accelerator compiler for the venice Vector Processor
    Field Programmable Gate Arrays, 2012
    Co-Authors: Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G.f. Lemieux
    Abstract:

    This paper describes the compiler design for VENICE, a new soft Vector Processor (SVP). The compiler is a new back-end target for Microsoft Accelerator, a high-level data parallel library for C++ and C#. This allows us to automatically compile high-level programs into VENICE assembly code, thus avoiding the process of writing assembly code used by previous SVPs. Experimental results show the compiler can generate scalable parallel code with execution times that are comparable to hand-written VENICE assembly code. On data-parallel applications, VENICE at 100MHz on an Altera DE3 platform runs at speeds comparable to one core of a 3.5GHz Intel Xeon W3690 Processor, beating it in performance on four of six benchmarks by up to 3.2x.

  • venice a compact Vector Processor for fpga applications
    IEEE Hot Chips Symposium, 2011
    Co-Authors: Aaron Severance, Guy G.f. Lemieux
    Abstract:

    This article consists of a collection of slides from the author's conference presentation on VENICE (Vector Extensions to NIOS Implemented Compactly and Elegantly), a SVP (soft Vector Processor) intended to accelerate computationally intensive applications implemented on an FPGA. SVPs are exclusively for FPGAs, targeted at the productivity gap between writing custom hardware in an HDL and writing software for a soft Processor in FPGA-based applications. They provide the convenience of software programming and software compile times, and yet they can achieve over 200x speedup compared to a scalar soft Processor.

  • vegas soft Vector Processor with scratchpad memory
    Field Programmable Gate Arrays, 2011
    Co-Authors: Christopher Han-yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G.f. Lemieux
    Abstract:

    This paper presents VEGAS, a new soft Vector architecture, in which the Vector Processor reads and writes directly to a scratchpad memory instead of a Vector register file. The scratchpad memory is a more efficient storage medium than a Vector register file, allowing up to 9x more data elements to fit into on-chip memory. In addition, the use of fracturable ALUs in VEGAS allow efficient processing of bytes, halfwords and words in the same Processor instance, providing up to 4x the operations compared to existing fixed-width soft Vector ALUs. Benchmarks show the new VEGAS architecture is 10x to 208x faster than Nios II and has 1.7x to 3.1x better area-delay product than previous Vector work, achieving much higher throughput per unit area. To put this performance in perspective, VEGAS is faster than a leading-edge Intel Processor at integer matrix multiply. To ease programming effort and provide full debug support, VEGAS uses a C macro API that outputs Vector instructions as standard NIOS II/f custom instructions.

  • Vector processing as a soft Processor accelerator
    ACM Transactions on Reconfigurable Technology and Systems, 2009
    Co-Authors: Christpher Eagleston, Christopher Han-yu Chou, Maxime Perreault, Guy G.f. Lemieux
    Abstract:

    Current FPGA soft Processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft Vector Processor as a general-purpose accelerator. The approach has the benefits of a purely software-oriented development model, a fixed ISA allowing parallel software and hardware development, a single accelerator that can accelerate multiple applications, and scalable performance from the same source code. With no hardware design experience needed, a software programmer can make area-versus-performance trade-offs by scaling the number of functional units and register file bandwidth with a single parameter. A soft Vector Processor can be further customized by a number of secondary parameters to add or remove features for a specific application to optimize resource utilization. This article introduces VIPERS, a soft Vector Processor architecture that maps efficiently into an FPGA and provides a scalable amount of performance for a reasonable amount of area. Compared to a Nios II/s Processor, instances of VIPERS with 32 processing lanes achieve up to 44× speedup using up to 26× the area.

Pi-feng Chiu - One of the best experts on this subject based on the ideXlab platform.

  • a dual core risc v Vector Processor with on chip fine grain power management in 28 nm fd soi
    IEEE Transactions on Very Large Scale Integration Systems, 2020
    Co-Authors: John Wright, Jaehwa Kwak, Ben Keller, Stevo Bailey, Pi-feng Chiu, Colin Schmidt, Daniel Dabbelt, Vighnesh Iyer, Nandish Mehta, Krste Asanovic
    Abstract:

    This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates switched-capacitor voltage converters and 4-Gb/s off-chip serial links. The SoC runs applications with operating system support on dual RISC-V Rocket cores with Vector accelerators. Runtime monitoring of microarchitectural counters allows prediction of future compute intensity, enabling the voltage state of the managed core to be adjusted quickly to optimize energy efficiency without sacrificing overall performance.

  • a risc v Vector Processor with simultaneous switching switched capacitor dc dc converters in 28 nm fdsoi
    IEEE Journal of Solid-state Circuits, 2016
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Milovan Blagojevic, Pi-feng Chiu, Steven Bailey, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

  • A RISC-V Vector Processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
    2015 Symposium on VLSI Circuits (VLSI Circuits), 2015
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-feng Chiu, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

  • Raven: A 28nm RISC-V Vector Processor with integrated switched-capacitor DC-DC converters and adaptive clocking
    2015 IEEE Hot Chips 27 Symposium (HCS), 2015
    Co-Authors: Yunsup Lee, Brian Zimmer, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Andrew Waterman, Pi-feng Chiu
    Abstract:

    This article consists of a collection of slides from the authors' conference presentation. The topics discussed included: Motivation/Raven Project Goals; On-Chip Switched Capacitor DC-DC Converters; Raven3 Chip Architecture; Raven3 Implementation; Raven3 Evaluation; and RISC-V Chip Building at UC Berkeley.

Brian Zimmer - One of the best experts on this subject based on the ideXlab platform.

  • a risc v Vector Processor with simultaneous switching switched capacitor dc dc converters in 28 nm fdsoi
    IEEE Journal of Solid-state Circuits, 2016
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Milovan Blagojevic, Pi-feng Chiu, Steven Bailey, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

  • A RISC-V Vector Processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
    2015 Symposium on VLSI Circuits (VLSI Circuits), 2015
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-feng Chiu, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

  • Raven: A 28nm RISC-V Vector Processor with integrated switched-capacitor DC-DC converters and adaptive clocking
    2015 IEEE Hot Chips 27 Symposium (HCS), 2015
    Co-Authors: Yunsup Lee, Brian Zimmer, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Andrew Waterman, Pi-feng Chiu
    Abstract:

    This article consists of a collection of slides from the authors' conference presentation. The topics discussed included: Motivation/Raven Project Goals; On-Chip Switched Capacitor DC-DC Converters; Raven3 Chip Architecture; Raven3 Implementation; Raven3 Evaluation; and RISC-V Chip Building at UC Berkeley.

Ben Keller - One of the best experts on this subject based on the ideXlab platform.

  • a dual core risc v Vector Processor with on chip fine grain power management in 28 nm fd soi
    IEEE Transactions on Very Large Scale Integration Systems, 2020
    Co-Authors: John Wright, Jaehwa Kwak, Ben Keller, Stevo Bailey, Pi-feng Chiu, Colin Schmidt, Daniel Dabbelt, Vighnesh Iyer, Nandish Mehta, Krste Asanovic
    Abstract:

    This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates switched-capacitor voltage converters and 4-Gb/s off-chip serial links. The SoC runs applications with operating system support on dual RISC-V Rocket cores with Vector accelerators. Runtime monitoring of microarchitectural counters allows prediction of future compute intensity, enabling the voltage state of the managed core to be adjusted quickly to optimize energy efficiency without sacrificing overall performance.

  • a risc v Vector Processor with simultaneous switching switched capacitor dc dc converters in 28 nm fdsoi
    IEEE Journal of Solid-state Circuits, 2016
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Milovan Blagojevic, Pi-feng Chiu, Steven Bailey, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

  • A RISC-V Vector Processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
    2015 Symposium on VLSI Circuits (VLSI Circuits), 2015
    Co-Authors: Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-feng Chiu, Po-hung Chen
    Abstract:

    This work demonstrates a RISC-V Vector microProcessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

  • Raven: A 28nm RISC-V Vector Processor with integrated switched-capacitor DC-DC converters and adaptive clocking
    2015 IEEE Hot Chips 27 Symposium (HCS), 2015
    Co-Authors: Yunsup Lee, Brian Zimmer, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Andrew Waterman, Pi-feng Chiu
    Abstract:

    This article consists of a collection of slides from the authors' conference presentation. The topics discussed included: Motivation/Raven Project Goals; On-Chip Switched Capacitor DC-DC Converters; Raven3 Chip Architecture; Raven3 Implementation; Raven3 Evaluation; and RISC-V Chip Building at UC Berkeley.