Vertical Interconnects

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Linda P. B. Katehi - One of the best experts on this subject based on the ideXlab platform.

  • 3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N
    IEEE Transactions on Microwave Theory and Techniques, 2010
    Co-Authors: Rosa R. Lahiji, Linda P. B. Katehi, Hasan Sharifi, Saeed Mohammadi
    Abstract:

    Parylene-N is used as a dielectric layer to create ultra low-loss 3-D Vertical Interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D Vertical interconnect through a 15-? m-thick parylene-N layer and 0.56 dB/mm for a 50-? CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with under passes that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-?m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of +4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.

  • Low-Loss Coplanar Waveguide Transmission Lines and Vertical Interconnects on Multi-Layer Parylene-N
    2009 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009
    Co-Authors: Rosa R. Lahiji, Saeed Mohammadi, Hasan Sharifi, Linda P. B. Katehi
    Abstract:

    Coplanar waveguide transmission lines and Vertical Interconnects are implemented on a thick (15µm) Parylene-N dielectric layer over a lossy CMOS-grade Si substrate. Devices are measured up to 40GHz and show very low loss behavior. Low loss tangent and low dielectric constant characteristics of Parylene-N result in significant improvement of transmission lines and Interconnects compared to those implemented in a standard Si integrated circuit technology.

  • Multiwafer Vertical Interconnects for three-dimensional integrated circuits
    IEEE Transactions on Microwave Theory and Techniques, 2006
    Co-Authors: Rosa R. Lahiji, K J Herrick, Yongshik Lee, Alexandros Margomenos, Saeed Mohammadi, Linda P. B. Katehi
    Abstract:

    Low-loss multiwafer Vertical Interconnects appropriate for a microstrip-based circuit architecture are proposed. These transitions have been designed, fabricated, and measured for 100-mum-thick silicon and GaAs substrates separately. Experimental results show excellent performance up to 20 GHz, with extremely low insertion loss (better than 0.12 and 0.38 dB for the two different silicon designs and 0.2 dB for the GaAs transition), and very good return loss (reflection of better than 12.9 and 17.3 dB for the two silicon designs, respectively, and 13.6 dB for the GaAs design). Using a high-performance transition allows for a more power-efficient interconnect, while it enables denser packaging by stacking the substrates on top of each other, as today's technologies demand

  • Low loss multi-wafer Vertical Interconnects for three dimensional integrated circuits
    2005 European Microwave Conference, 2005
    Co-Authors: Rosa R. Lahiji, K J Herrick, Saeed Mohammadi, Linda P. B. Katehi
    Abstract:

    A low loss multi-wafer Vertical interconnect appropriate for a microstrip-based circuit architecture is proposed. This transition has been designed, fabricated and measured on 100 /spl mu/m thick GaAs substrates. The measurements demonstrate insertion loss of better than 0.2dB and reflection of better than 13.6dB up to 20GHz. Using such a high performance transition allows for a more power efficient interconnect, while it enables denser packaging by stacking the substrates on top of each other, as today's technologies demand.

  • microtechnology in the development of three dimensional circuits
    IEEE Transactions on Microwave Theory and Techniques, 1998
    Co-Authors: K J Herrick, Jong-gwan Yook, Linda P. B. Katehi
    Abstract:

    With today's cost-conscience industry, low cost, high-performance, and high-profit microwave-circuit technologies are essential. To increase density and reduce size and cost, the integration of analog and digital circuits on one single chip is considered the most viable solution. In reducing the size of the overall system, high-density integration (HDI) and packaging have become critical components in circuit design. This paper reviews and evaluates state-of-the-art planar transmission lines and Vertical Interconnects for use in high-density multilayer circuits for silicon- and SiGe-based monolithic high-frequency circuits. Packaging issues associated with parasitics are discussed and examples of multilayer three-dimensional systems utilizing micromachining are presented.

Sanjay Raman - One of the best experts on this subject based on the ideXlab platform.

  • liquid metal Vertical Interconnects for flip chip assembly of gaas c band power amplifiers onto micro rectangular coaxial transmission lines
    IEEE Journal of Solid-state Circuits, 2012
    Co-Authors: Parrish Ralston, Krishna Vummidi, Marcus Oliver, Sanjay Raman
    Abstract:

    Prior work has demonstrated a new process utilizing room-temperature liquid metal, Galinstan, as an interconnect material for flip-chip bonding. This interconnect forms a flexible bond between chips and carriers, and, therefore, a flip-chip assembly using this technology is much less susceptible to thermomechanical stresses. This paper applies this concept to interconnect GaAs MMIC chips to 3-D Polystrata transmission-line structures. Passive assemblies are utilized to model, test, and verify liquid-metal interconnections, giving average losses per liquid-metal transition of about 0.11 dB out to 26.5 GHz, low parasitics per transition, and demonstrated reliability after temperature cycling. A prefabricated GaAs MMIC chip is postprocessed for liquid-metal assembly. Measured results show, over the MMIC's 4.9-8.5-GHz frequency range, the system's overall reduction in gain of the MMIC is 1.4 dB or 0.7 dB per RF transition as compared with direct probing of the MMIC chip.

  • liquid metal Vertical Interconnects for flip chip assembly of gaas c band power amplifiers onto micro rectangular coaxial transmission lines
    Compound Semiconductor Integrated Circuit Symposium, 2011
    Co-Authors: Parrish Ralston, Krishna Vummidi, Marcus Oliver, Sanjay Raman
    Abstract:

    Prior work has demonstrated a new process utilizing room temperature liquid metal, galinstan, as an interconnect material for flip chip bonding. This interconnect forms a flexible bond between chips and carriers and therefore a flip chip assembly using this technology is much less susceptible to thermomechanical stresses. This paper applies this concept to interconnect MMIC chips to 3D Polystrata transmission line structures. A prefabricated GaAs MMIC chip is post processed for liquid metal assembly. Measured results show, over the MMIC's 4.9 - 8.5 GHz frequency range, the system's overall reduction in gain of the MMIC is 1.4 dB or 0.7dB per RF transition as compared to direct probing of the MMIC chip.

  • Liquid metal Vertical Interconnects for RF flip-chip assembly
    2009 IEEE MTT-S International Microwave Symposium Digest, 2009
    Co-Authors: Joseph Wood, Krishna Vummidi, Parrish Ralston, Lihan Chen, N. Scott Barker, Sanjay Raman
    Abstract:

    This paper describes a new process for using room temperature liquid metals as the interconnect material for flip chip bonding. The proposed liquid metal Interconnects are not susceptible to damage caused by thermo-mechanical stress and are therefore an attractive alternative to solid phase solder bumps. A new interconnect structure is presented involving a patterned underfill dielectric material to contain the liquid metal on the bottom carrier, and electroplated pins on the top chip to mate with the socket and make contact with the liquid metal. RF and DC measurements were performed on the liquid metal transition showing an insertion loss of ≪0.5dB up to 20 GHz.

Sten Vollebregt - One of the best experts on this subject based on the ideXlab platform.

  • Carbon nanotubes as Vertical Interconnects in 3D integrated circuits
    Carbon Nanotubes for Interconnects, 2016
    Co-Authors: Sten Vollebregt
    Abstract:

    Interconnects in integrated circuits (IC) are the major cause of power dissipation and delay. 3D integration has been proposed as a method to reduce these issues. For this 3D integration, fabrication of high aspect ratio reliable Vertical Interconnects (vias) are required. For this new materials, like carbon nanotubes (CNT), are being considered due to their excellent electrical and thermal properties. In this thesis CNT are investigated for the use as via in 3D IC. Raman spectroscopy is investigated for determining the CNT quality. CNT are grown on electrically conductive TiN layers at record-low temperatures of 350 °C using Co as catalyst. On electrically conductive ZrN layers CNT bundles with lengths of several hundred micrometre could be grown using Fe as catalyst, which is to our knowledge the first example of ultra-long CNT on a conductive substrate. Electrical measurements were performed on CNT vias fabricated at 350-500 °C. The contact resistance, uniformity, electrical reliability, and resistivity were determined and compared to literature. The resistivity of 20 m?-cm is similar to values in literature, and high compared to that of Cu and Al due to the low quality and bundle density of the CNT. The thermal conductivity of the CNT bundles was also found to be low due to their low quality, and large thermal interface resistance between the CNT and metal. Finally, for the first time CNT were integrated directly with actual electronics, and 3D IC with two transistor layers were fabricated and characterised. The large CNT via resistance due to their low quality was found to limit the performance of the transistors. This indicates that the material properties of CNT should be improved considerably before they can be put to use in actual IC.

  • The direct growth of carbon nanotubes as Vertical Interconnects in 3D integrated circuits
    Carbon, 2016
    Co-Authors: Sten Vollebregt, Ryoichi Ishihara
    Abstract:

    Carbon nanotubes (CNT) have been proposed for many applications in integrated circuits (IC): ranging from transistors and Interconnects to sensors and actuators. For these applications it is crucial to integrate CNT directly alongside electronics, something which has not been achieved before. In this work we demonstrate the direct growth of CNT alongside CMOS devices, by integrating CNT as Vertical interconnect (vias) in a monolithic 3D IC process using techniques and materials compatible with semiconductor technology. The electrical performance of both the CNT vias and the electrical devices is investigated and compared with the literature. From this we can conclude that the CNT growth has no significant impact on the electrical devices, although the resistance of the CNT should be further reduced to compete with metal Interconnects. This demonstrates the viability of integrating CNT with IC, which is an important step forward in the application of CNT in electronics.

  • Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology.
    Journal of visualized experiments : JoVE, 2015
    Co-Authors: Sten Vollebregt, Ryoichi Ishihara
    Abstract:

    We demonstrate a method for the low temperature growth (350 °C) of Vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-κ dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for Vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates Vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test Vertical Interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

  • Carbon nanotube Vertical Interconnects fabricated at temperatures as low as 350 °C
    Carbon, 2014
    Co-Authors: Sten Vollebregt, C.i.m. Beenakker, H. Schellevis, Frans D. Tichelaar, Ryoichi Ishihara
    Abstract:

    Abstract Carbon nanotube (CNT) Vertical Interconnects (vias) were fabricated on conductive substrates at a record-low temperature of 350 °C, using only standard semiconductor manufacturing techniques and materials. CNT growth rates were investigated for both Co and a Co–Al alloy catalysts, and compared to that of Fe. The activation energy of the Co-based catalysts was found to be lower, allowing lower temperature growth. Using Co as catalyst full-wafer CNT test vias were fabricated at 350 °C, and 400 °C, and electrically characterized. Good uniformity was obtained, with no apparent yield-loss compared to higher temperature fabricated CNT vias. A negative thermal coefficient of resistance was observed of −800 ppm/K, which is advantageous for interconnect applications. The resistivity of the vias increases with temperature, up to 139 mΩ cm for 350 °C, but was found to be lower than several values obtained from literature of CNT vias fabricated at higher temperatures.

  • low temperature bottom up integration of carbon nanotubes for Vertical Interconnects in monolithic 3d integrated circuits
    IEEE International D Systems Integration Conference, 2012
    Co-Authors: Sten Vollebregt, Johan Van Der Cingel, Ryoichi Ishihara, Kees Beenakker
    Abstract:

    Carbon nanotubes (CNT) can be an attractive candidate for Vertical Interconnects in 3D monolithic integration, due to their excellent thermal and electrical properties. In this paper we investigate the use of a true bottom-up approach to fabricate CNT vias, for application in 3D monolithic integration. This circumvents metal deposition in high aspect ratio holes, and also allows the use of bundle densification techniques to increase CNT density. Using this approach we fabricated four-point probe electrical measurement structures for both as-grown and densified CNT bundles, and performed I-V measurements. The resulting I-V curves display non-linearities due to a non-Ohmic top contact. The measured resistivities of 10–20 mΩ-cm are among the better values found in literature.

Dago M. De Leeuw - One of the best experts on this subject based on the ideXlab platform.

  • high performance all polymer integrated circuits
    Applied Physics Letters, 2000
    Co-Authors: Gerwin H Gelinck, Tom C T Geuns, Dago M. De Leeuw
    Abstract:

    In this letter, we demonstrate the integration of all-polymer field-effect transistors in fully functional integrated circuits with operating frequencies of several kHz. One of the key items is an approach to incorporate low-Ohmic Vertical Interconnects compatible with an all-polymer approach. Inverters, NAND gates, and ring oscillators with transistor channel lengths down to 1 μm have been constructed. Inverters show voltage amplification at moderate biases and pentacene seven-stage ring oscillators show switching frequencies of a few kHz. The potential to realize large integrated circuits is demonstrated by a 15 bit code generator circuit using several hundreds of devices. The proposed concept was evaluated for three solution-processable organic semiconductors.

  • low cost all polymer integrated circuits
    Applied Physics Letters, 1998
    Co-Authors: Christopher John Drury, C M J Mutsaers, Cornelis Maria Hart, Marco Matters, Dago M. De Leeuw
    Abstract:

    A technology has been developed to make all polymer integrated circuits. It involves reproducible fabrication of field-effect transistors in which the semiconducting, conducting and insulating parts are all made of polymers. The fabrication on flexible substrates uses spin-coating of electrically active precursors and patternwise exposure of the deposited films. In the whole process stack integrity is maintained. Vertical Interconnects are made mechanically. As a demonstrator functional 15-bit programmable code generators are fabricated. These circuits still operate when the foils are sharply bent. Due to the limited number of process steps the technology is potentially inexpensive.

Ryoichi Ishihara - One of the best experts on this subject based on the ideXlab platform.

  • The direct growth of carbon nanotubes as Vertical Interconnects in 3D integrated circuits
    Carbon, 2016
    Co-Authors: Sten Vollebregt, Ryoichi Ishihara
    Abstract:

    Carbon nanotubes (CNT) have been proposed for many applications in integrated circuits (IC): ranging from transistors and Interconnects to sensors and actuators. For these applications it is crucial to integrate CNT directly alongside electronics, something which has not been achieved before. In this work we demonstrate the direct growth of CNT alongside CMOS devices, by integrating CNT as Vertical interconnect (vias) in a monolithic 3D IC process using techniques and materials compatible with semiconductor technology. The electrical performance of both the CNT vias and the electrical devices is investigated and compared with the literature. From this we can conclude that the CNT growth has no significant impact on the electrical devices, although the resistance of the CNT should be further reduced to compete with metal Interconnects. This demonstrates the viability of integrating CNT with IC, which is an important step forward in the application of CNT in electronics.

  • Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology.
    Journal of visualized experiments : JoVE, 2015
    Co-Authors: Sten Vollebregt, Ryoichi Ishihara
    Abstract:

    We demonstrate a method for the low temperature growth (350 °C) of Vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-κ dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for Vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates Vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test Vertical Interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

  • Carbon nanotube Vertical Interconnects fabricated at temperatures as low as 350 °C
    Carbon, 2014
    Co-Authors: Sten Vollebregt, C.i.m. Beenakker, H. Schellevis, Frans D. Tichelaar, Ryoichi Ishihara
    Abstract:

    Abstract Carbon nanotube (CNT) Vertical Interconnects (vias) were fabricated on conductive substrates at a record-low temperature of 350 °C, using only standard semiconductor manufacturing techniques and materials. CNT growth rates were investigated for both Co and a Co–Al alloy catalysts, and compared to that of Fe. The activation energy of the Co-based catalysts was found to be lower, allowing lower temperature growth. Using Co as catalyst full-wafer CNT test vias were fabricated at 350 °C, and 400 °C, and electrically characterized. Good uniformity was obtained, with no apparent yield-loss compared to higher temperature fabricated CNT vias. A negative thermal coefficient of resistance was observed of −800 ppm/K, which is advantageous for interconnect applications. The resistivity of the vias increases with temperature, up to 139 mΩ cm for 350 °C, but was found to be lower than several values obtained from literature of CNT vias fabricated at higher temperatures.

  • low temperature bottom up integration of carbon nanotubes for Vertical Interconnects in monolithic 3d integrated circuits
    IEEE International D Systems Integration Conference, 2012
    Co-Authors: Sten Vollebregt, Johan Van Der Cingel, Ryoichi Ishihara, Kees Beenakker
    Abstract:

    Carbon nanotubes (CNT) can be an attractive candidate for Vertical Interconnects in 3D monolithic integration, due to their excellent thermal and electrical properties. In this paper we investigate the use of a true bottom-up approach to fabricate CNT vias, for application in 3D monolithic integration. This circumvents metal deposition in high aspect ratio holes, and also allows the use of bundle densification techniques to increase CNT density. Using this approach we fabricated four-point probe electrical measurement structures for both as-grown and densified CNT bundles, and performed I-V measurements. The resulting I-V curves display non-linearities due to a non-Ohmic top contact. The measured resistivities of 10–20 mΩ-cm are among the better values found in literature.

  • Electrical characterization of carbon nanotube Vertical Interconnects with different lengths and widths
    2012 IEEE International Interconnect Technology Conference, 2012
    Co-Authors: Sten Vollebregt, Johan Van Der Cingel, Ryoichi Ishihara, Frans D. Tichelaar, Kees Beenakker
    Abstract:

    Carbon nanotubes (CNT) can be an attractive candidate for Vertical Interconnects due to their bottom-up nature and excellent electrical and thermal properties. In this paper we demonstrate low temperature high-density CNT growth and results of electrical characterization. We determined that our CNT contact resistance is low compared to other results in literature, likely caused by a good top contact. The CNT display good uniformity over the wafer and the calculated resistivity of 10 mΩ-cm is among the lowest in literature.