The Experts below are selected from a list of 1077 Experts worldwide ranked by ideXlab platform
Hideharu Amano - One of the best experts on this subject based on the ideXlab platform.
-
FPL - Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –
Field Programmable Logic and Application, 2004Co-Authors: Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu SuzukiAbstract:Virtual Hardware is difficult to implement even on recent dynamically reconfigurable processors when the loop body of the target application cannot be stored in the set of quickly switch-able contexts. Here, techniques for such tough cases are proposed. Differential configuration which changes only different parts of similar contexts can drastically reduce the time for re-configuration. Pairwise context assignment policy can hide the overhead of configuration with double buffering. Out-of-order context switching enables execution of available context in advance. Through an implementation example on NEC’s DRP-1, it appears that the Virtual Hardware can be executed with practical speed by combining the proposed techniques.
-
techniques for Virtual Hardware on a dynamically reconfigurable processor an approach to tough cases
Lecture Notes in Computer Science, 2004Co-Authors: Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu SuzukiAbstract:Virtual Hardware is difficult to implement even on recent dynamically reconfigurable processors when the loop body of the target application cannot be stored in the set of quickly switch-able contexts. Here, techniques for such tough cases are proposed. Differential configuration which changes only different parts of similar contexts can drastically reduce the time for re-configuration. Pairwise context assignment policy can hide the overhead of configuration with double buffering. Out-of-order context switching enables execution of available context in advance. Through an implementation example on NEC's DRP-1, it appears that the Virtual Hardware can be executed with practical speed by combining the proposed techniques.
-
ASP-DAC - A prototype chip of multicontext FPGA with DRAM for Virtual Hardware
Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001Co-Authors: Daisuke Kawakami, Yuichro Shibata, Hideharu AmanoAbstract:DRAM-type multicontext FPGA has potential for Virtual Hardware, since it is possible to implement a large number of contexts in a single chip. However, only a few examples have been reported because of the difficulty of the mixed process involving DRAM and logic. Here we try to implement a prototype multicontext FPGA with DRAM for Virtual Hardware.
-
FPL - Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware
Lecture Notes in Computer Science, 2000Co-Authors: Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu AmanoAbstract:This paper presents a new dataflow graph partitioning algorithm for a data driven Virtual Hardware system called WASMII. The algorithm divides a dataflow graph into multiple subgraphs so as not to cause a deadlock. Then the subgraphs are translated into an FPGA configuration and executed on WASMII in a time-multiplexed manner. The experimental results show the proposed algorithms can achieve 13% to 39% improvement of execution performance compared to other existing graph partitioning algorithms at the most.
-
FCCM - A Virtual Hardware system on a dynamically reconfigurable logic device
Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871), 2000Co-Authors: Yuichiro Shibata, Hideharu Amano, Taro Fujii, K. Furuta, Masato MotomuraAbstract:WASMII is Virtual Hardware using a multi-context reconfigurable device with a data driven control. Since implementation of WASMII was infeasible due to the unavailability of such a device, the system has been only evaluated using an emulator so far. However, the first reconfigurable multi-context device called DRL has been developed by NEC. Making the use of its flexible reconfigurability, we have implemented a mechanism of WASMII on DRL.
Hongtao Guan - One of the best experts on this subject based on the ideXlab platform.
-
Building a Flexible and Scalable Virtual Hardware Data Plane
2012Co-Authors: Junjie Liu, Yingke Xie, Fuxing Zhang, Layong Luo, Qingsong Ning, Xiaolong Wu, Gaogang Xie, Hongtao GuanAbstract:Network Virtualization which enables the coexistence of multiple networks in shared infrastructure adds extra requirements on data plane of router. Software based Virtual data plane is inferior in performance, whereas, Hardware based Virtual data plane is hard to achieve flexibility and scalability. In this paper, using FPGA (Field Program Gate Array) and TCAM (Ternary Content Addressable Memory), we design and implement a Virtual Hardware data plane achieving high performance, flexibility and scalability simultaneously. The data plane uses a 5-stage pipeline design. The procedure of packet processing is unified with TCAM based rule matching and action based packet processing. The Hardware data plane can be easily configured to support multiple VDP (Virtual Data Plane) instances. And in each VDP instance, the pattern of packet processing can be flexibly configured. Also, it can achieve seamless migration of VDP instance between software and Hardware. The Hardware data plane also provides a 4-channel high-performance DMA engine which largely reduces packet acquisition overhead on software. So that software can be more involved in customized packet processing.
-
Networking (1) - Building a flexible and scalable Virtual Hardware data plane
NETWORKING 2012, 2012Co-Authors: Fuxing Zhang, Qingsong Ning, Xiaolong Wu, Hongtao GuanAbstract:Network Virtualization which enables the coexistence of multiple networks in shared infrastructure adds extra requirements on data plane of router. Software based Virtual data plane is inferior in performance, whereas, Hardware based Virtual data plane is hard to achieve flexibility and scalability. In this paper, using FPGA (Field Program Gate Array) and TCAM (Ternary Content Addressable Memory), we design and implement a Virtual Hardware data plane achieving high performance, flexibility and scalability simultaneously. The data plane uses a 5-stage pipeline design. The procedure of packet processing is unified with TCAM based rule matching and action based packet processing. The Hardware data plane can be easily configured to support multiple VDP (Virtual Data Plane) instances. And in each VDP instance, the pattern of packet processing can be flexibly configured. Also, it can achieve seamless migration of VDP instance between software and Hardware. The Hardware data plane also provides a 4-channel high-performance DMA engine which largely reduces packet acquisition overhead on software. So that software can be more involved in customized packet processing.
Steven D Grible - One of the best experts on this subject based on the ideXlab platform.
-
constructing services with interposable Virtual Hardware
Networked Systems Design and Implementation, 2004Co-Authors: Andrew Whitaker, Marianne Shaw, Steven D GribleAbstract:Virtual machine monitors (VMMs) have enjoyed a resurgence in popularity, since VMMs can help to solve difficult systems problems like migration, fault tolerance, code sandboxing, intrusion detection, and debugging. Recently, several researchers have proposed novel applications of Virtual machine technology, such as Internet Suspend/Resume [25, 31] and transparent OS-level rollback and replay [13]. Unfortunately, current VMMs do not export enough functionality to budding developers of such applications, forcing them either to reverse engineer pieces of a black-box VMM, or to reimplement significant portions of a VMM. In this paper, we present the design, implementation, and evaluation of µDenali, an extensible and programmable Virtual machine monitor that has the ability to run modern operating systems. µDenali allows programmers to extend the Virtual architecture exposed by the VMM to a Virtual machine, in effect giving systems programmers the ability to dynamically assemble a Virtual machine out of either default or custom-built Virtual Hardware elements. µDenali allows programmers to interpose on and modify events at the level of the Virtual architecture, enabling them to easily perform tasks such as manipulating disk and network events, or capturing and migrating Virtual machine state. In addition to describing and evaluating our extensible Virtual machine monitor, we present an application-level API that simplifies writing extensions, and we discuss applications of Virtual machines that we have built using this API.
-
NSDI - Constructing services with interposable Virtual Hardware
2004Co-Authors: Andrew Whitaker, Marianne Shaw, Steven D GribleAbstract:Virtual machine monitors (VMMs) have enjoyed a resurgence in popularity, since VMMs can help to solve difficult systems problems like migration, fault tolerance, code sandboxing, intrusion detection, and debugging. Recently, several researchers have proposed novel applications of Virtual machine technology, such as Internet Suspend/Resume [25, 31] and transparent OS-level rollback and replay [13]. Unfortunately, current VMMs do not export enough functionality to budding developers of such applications, forcing them either to reverse engineer pieces of a black-box VMM, or to reimplement significant portions of a VMM. In this paper, we present the design, implementation, and evaluation of µDenali, an extensible and programmable Virtual machine monitor that has the ability to run modern operating systems. µDenali allows programmers to extend the Virtual architecture exposed by the VMM to a Virtual machine, in effect giving systems programmers the ability to dynamically assemble a Virtual machine out of either default or custom-built Virtual Hardware elements. µDenali allows programmers to interpose on and modify events at the level of the Virtual architecture, enabling them to easily perform tasks such as manipulating disk and network events, or capturing and migrating Virtual machine state. In addition to describing and evaluating our extensible Virtual machine monitor, we present an application-level API that simplifies writing extensions, and we discuss applications of Virtual machines that we have built using this API.
Xiao Ping Ling - One of the best experts on this subject based on the ideXlab platform.
-
ICPP Workshops - Implementation and evaluation of the compiler for WASMII, a Virtual Hardware system
Proceedings of the 1999 ICPP Workshops on Collaboration and Mobile Computing (CMC'99). Group Communications (IWGC). Internet '99 (IWI'99). Industrial , 1999Co-Authors: Atsushi Takayama, Yuichiro Shibata, Hidenori Miyazaki, Keisuke Iwai, K. Higure, Xiao Ping LingAbstract:WASMII is a reconfigurable system with data driven control which executes programs written in dataflow graphs. In WASMII, a target dataflow graph is divided into some subgraphs and executed on a programmable device called MPLD which is an extended FPGA. By replacing the configuration data on the MPLD, large scale programs which exceed the limit of Hardware resources can be efficiently executed. As a software environment of WASMII, a compiler which translates a program written by a user in a high-level language into a corresponding dataflow graph and its HDL description is required. In this paper we show the design and implementation of the compiler for WASMII which generates the VHDL description from an input program. Compilation and execution results of a test program on a reconfigurable testbed called FLEMING are also shown.
-
IPPS/SPDP Workshops - HOSMII: A Virtual Hardware integrated with DRAM
Lecture Notes in Computer Science, 1998Co-Authors: Yuichiro Shibata, Hidenori Miyazaki, Xiao Ping Ling, Hideharu AmanoAbstract:WASMII, a Virtual Hardware system that executes dataflow algorithms, is based on an MPLD, an extended FPGA with multiple sets of configuration SRAM. Although we have developed an emulation system and software environment for WASMII, it has tended to be unrealistic due to the difficulty of the MPLD implementation. However, with recent technologies of semiconductors, an FPGA and DRAM can be implemented into a single LSI chip. We propose novel Virtual Hardware called HOSMII using such an FPGA/DRAM chip which can hold hundreds of configuration data and switch them instantaneously.
-
Towards the realistic "Virtual Hardware"
Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997Co-Authors: Yuichiro Shibata, Hidenori Miyazaki, Xiao Ping Ling, Hideharu AmanoAbstract:WASMII is a Virtual Hardware system that executes dataflow algorithms. It is based on an MPLD (Multifunction Programming Logic Device), an extended FPGA (Field Programmable Gate Array) that implements multiple sets of functions as configurations of a single chip. An algorithm to be executed on WASMII is written in the DFC dataflow language and then translated into a collection of FPGA configurations, each representing a page-sized subgraph of the dataflow graph. Although we have developed an emulation system and software environment for WASMII, it has tended to be an unrealistic system due to the difficulty of the MPLD implementation. However with recent technologies of semiconductors, FPGA and DRAM can be implemented into a single LSI chip. By using the column buffer of the DRAM array as a configuration memory of an FPGA, replacement of configuration data can be done almost the same speed as an MPLD. Compared with the MPLD approach, a large amount of data can be stored in the integrated DRAM. Initial simulation results show that such a chip can almost save the loss caused by data transfer from the off chip memory of original WASMII.
-
FPL - An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware
Lecture Notes in Computer Science, 1996Co-Authors: Yuichiro Shibata, Xiao Ping Ling, Hideharu AmanoAbstract:WASMII is a Virtual Hardware system which exploits dynamically reconfigurable FPGAs with a data driven control mechanism. In this paper, an emulation system of the WASMII is proposed and designed. A Virtual Hardware mechanism is emulated by using two FPGAs which can be on-the-fly partial reconfiguration. In the system, all configuration data which is not activated is stored in the off-chip backup RAMs and loaded into the FPGA on demand as well as Virtual memory. The control units of this system are synthesized with approximately 1,500 gates from a VHDL description, and analyzed by a simulation tool. Through the analysis, it is shown that by making the best use of the Hardware table and register structure tailored to each application, the system works at 10 MHz. Executing results of simple non-linear system simulation are also presented.
-
WASMII: An MPLD with data-driven control on a Virtual Hardware
The Journal of Supercomputing, 1995Co-Authors: Xiao Ping Ling, Hideharu AmanoAbstract:Through the use of an extended field programmable gate array (FPGA) technology, a large digital circuit can be realized on a relatively small amount of real Hardware. Several configuration RAM modules are provided inside the FPGA chip, and the configuration of the gate array can be rapidly changed by replacing the active module. Data for configuration are transferred from an off-chip backup RAM to an unused configuration RAM module. A novel computation mechanism called the WASMII, which executes a target dataflow graph directly, can be proposed on the basis of this “Virtual Hardware.” A WASMII chip consists of the FPGA for Virtual Hardware and an additional mechanism to replace configuration RAM modules in a data-driven manner. Configuration data are preloaded in the order assigned in advance by a static scheduling preprocessor. By connecting a number of WASMII chips, a highly parallel system can be easily constructed.
Masayasu Suzuki - One of the best experts on this subject based on the ideXlab platform.
-
FPL - Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –
Field Programmable Logic and Application, 2004Co-Authors: Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu SuzukiAbstract:Virtual Hardware is difficult to implement even on recent dynamically reconfigurable processors when the loop body of the target application cannot be stored in the set of quickly switch-able contexts. Here, techniques for such tough cases are proposed. Differential configuration which changes only different parts of similar contexts can drastically reduce the time for re-configuration. Pairwise context assignment policy can hide the overhead of configuration with double buffering. Out-of-order context switching enables execution of available context in advance. Through an implementation example on NEC’s DRP-1, it appears that the Virtual Hardware can be executed with practical speed by combining the proposed techniques.
-
techniques for Virtual Hardware on a dynamically reconfigurable processor an approach to tough cases
Lecture Notes in Computer Science, 2004Co-Authors: Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu SuzukiAbstract:Virtual Hardware is difficult to implement even on recent dynamically reconfigurable processors when the loop body of the target application cannot be stored in the set of quickly switch-able contexts. Here, techniques for such tough cases are proposed. Differential configuration which changes only different parts of similar contexts can drastically reduce the time for re-configuration. Pairwise context assignment policy can hide the overhead of configuration with double buffering. Out-of-order context switching enables execution of available context in advance. Through an implementation example on NEC's DRP-1, it appears that the Virtual Hardware can be executed with practical speed by combining the proposed techniques.
