The Experts below are selected from a list of 324 Experts worldwide ranked by ideXlab platform
Daniele Venturi - One of the best experts on this subject based on the ideXlab platform.
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a tamper and leakage resilient Von Neumann Architecture
Public Key Cryptography, 2015Co-Authors: Sebastian Faust, Pratyay Mukherjee, Jesper Buus Nielsen, Daniele VenturiAbstract:We present a universal framework for tamper and leakage resilient computation on a random access machine (RAM). The RAM has one CPU that accesses a storage, which we call the disk. The disk is subject to leakage and tampering. So is the bus connecting the CPU to the disk. We assume that the CPU is leakage and tamper-free. For a fixed value of the security parameter, the CPU has constant size. Therefore the code of the program to be executed is stored on the disk, i.e., we consider a Von Neumann Architecture. The most prominent consequence of this is that the code of the program executed will be subject to tampering.
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Public Key Cryptography - A Tamper and Leakage Resilient Von Neumann Architecture
Lecture Notes in Computer Science, 2015Co-Authors: Sebastian Faust, Pratyay Mukherjee, Jesper Buus Nielsen, Daniele VenturiAbstract:We present a universal framework for tamper and leakage resilient computation on a random access machine (RAM). The RAM has one CPU that accesses a storage, which we call the disk. The disk is subject to leakage and tampering. So is the bus connecting the CPU to the disk. We assume that the CPU is leakage and tamper-free. For a fixed value of the security parameter, the CPU has constant size. Therefore the code of the program to be executed is stored on the disk, i.e., we consider a Von Neumann Architecture. The most prominent consequence of this is that the code of the program executed will be subject to tampering.
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a tamper and leakage resilient Von Neumann Architecture
2015Co-Authors: Sebastian Faust, Pratyay Mukherjee, Jesper Buus Nielsen, Daniele VenturiAbstract:We present a universal framework for tamper and leakage resilient computation on a Von Neumann Random Access Architecture (RAM in short). The RAM has one CPU that accesses a storage, which we call the disk. The disk is subject to leakage and tampering. So is the bus connecting the CPU to the disk. We assume that the CPU is leakage and tamper-free. For a fixed value of the security parameter, the CPU has constant size. Therefore the code of the program to be executed is stored on the disk, i.e., we consider a Von Neumann Architecture. The most prominent consequence of this is that the code of the program executed will be subject to tampering. We construct a compiler for this Architecture which transforms any keyed primitive into a RAM program where the key is encoded and stored on the disk along with the program to evaluate the primitive on that key. Our compiler only assumes the existence of a so-called continuous non-malleable code, and it only needs black-box access to such a code. No further (cryptographic) assumptions are needed. This in particular means that given an information theoretic code, the overall construction is information theoretic secure. Although it is required that the CPU is tamper and leakage proof, its design is independent of the actual primitive being computed and its internal storage is non-persistent, i.e., all secret registers are reset between invocations. Hence, our result can be interpreted as reducing the problem of shielding arbitrary complex computations to protecting a single, simple yet universal component.
Sebastian Faust - One of the best experts on this subject based on the ideXlab platform.
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a tamper and leakage resilient Von Neumann Architecture
Public Key Cryptography, 2015Co-Authors: Sebastian Faust, Pratyay Mukherjee, Jesper Buus Nielsen, Daniele VenturiAbstract:We present a universal framework for tamper and leakage resilient computation on a random access machine (RAM). The RAM has one CPU that accesses a storage, which we call the disk. The disk is subject to leakage and tampering. So is the bus connecting the CPU to the disk. We assume that the CPU is leakage and tamper-free. For a fixed value of the security parameter, the CPU has constant size. Therefore the code of the program to be executed is stored on the disk, i.e., we consider a Von Neumann Architecture. The most prominent consequence of this is that the code of the program executed will be subject to tampering.
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Public Key Cryptography - A Tamper and Leakage Resilient Von Neumann Architecture
Lecture Notes in Computer Science, 2015Co-Authors: Sebastian Faust, Pratyay Mukherjee, Jesper Buus Nielsen, Daniele VenturiAbstract:We present a universal framework for tamper and leakage resilient computation on a random access machine (RAM). The RAM has one CPU that accesses a storage, which we call the disk. The disk is subject to leakage and tampering. So is the bus connecting the CPU to the disk. We assume that the CPU is leakage and tamper-free. For a fixed value of the security parameter, the CPU has constant size. Therefore the code of the program to be executed is stored on the disk, i.e., we consider a Von Neumann Architecture. The most prominent consequence of this is that the code of the program executed will be subject to tampering.
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a tamper and leakage resilient Von Neumann Architecture
2015Co-Authors: Sebastian Faust, Pratyay Mukherjee, Jesper Buus Nielsen, Daniele VenturiAbstract:We present a universal framework for tamper and leakage resilient computation on a Von Neumann Random Access Architecture (RAM in short). The RAM has one CPU that accesses a storage, which we call the disk. The disk is subject to leakage and tampering. So is the bus connecting the CPU to the disk. We assume that the CPU is leakage and tamper-free. For a fixed value of the security parameter, the CPU has constant size. Therefore the code of the program to be executed is stored on the disk, i.e., we consider a Von Neumann Architecture. The most prominent consequence of this is that the code of the program executed will be subject to tampering. We construct a compiler for this Architecture which transforms any keyed primitive into a RAM program where the key is encoded and stored on the disk along with the program to evaluate the primitive on that key. Our compiler only assumes the existence of a so-called continuous non-malleable code, and it only needs black-box access to such a code. No further (cryptographic) assumptions are needed. This in particular means that given an information theoretic code, the overall construction is information theoretic secure. Although it is required that the CPU is tamper and leakage proof, its design is independent of the actual primitive being computed and its internal storage is non-persistent, i.e., all secret registers are reset between invocations. Hence, our result can be interpreted as reducing the problem of shielding arbitrary complex computations to protecting a single, simple yet universal component.
Mingoo Seok - One of the best experts on this subject based on the ideXlab platform.
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a near threshold spiking neural network accelerator with a body swapping based in situ error detection and correction technique
IEEE Transactions on Very Large Scale Integration Systems, 2019Co-Authors: Seongjong Kim, Joao P Cerqueira, Mingoo SeokAbstract:Specialized Architecture combined with near- and subthreshold voltage circuits emerges as a promising candidate to improve the energy efficiency in performing complex computing kernels in a resource-constrained device. One of the critical challenges in such design is the large delay variability across process, voltage, and temperature (PVT) variations. The in situ error detection and correction (EDAC) technique can potentially handle such variations; however, since existing techniques have targeted Von-Neumann Architecture and nominal voltage circuits, it becomes nontrivial to apply them on near and subthreshold voltage accelerators, many of which do not base on the Von-Neumann Architecture. In particular, those accelerators often have no instruction, making it difficult to use the popular instruction-replay-based error correction. To tackle this challenge, in this paper, we propose a novel in situ EDAC technique that utilizes dynamic, temporarily, and spatially fine-grained body swapping for error correction without instruction replay. Using the proposed technique, we prototyped a spiking neural network (SNN) sorter in non-Von-Neumann Architecture. The prototyped chip can successfully remove the worst-case margin and, thus, achieve 49.3% higher energy efficiency and 35.6% higher throughput compared to the baseline that operates with the worst-case margin. The proposed technique incurs only 4.1% silicon area overhead and requires no additional supply voltage.
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A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based $In \,\,Situ$ Error Detection and Correction Technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019Co-Authors: Seongjong Kim, Joao P Cerqueira, Mingoo SeokAbstract:Specialized Architecture combined with near- and subthreshold voltage circuits emerges as a promising candidate to improve the energy efficiency in performing complex computing kernels in a resource-constrained device. One of the critical challenges in such design is the large delay variability across process, voltage, and temperature (PVT) variations. The in situ error detection and correction (EDAC) technique can potentially handle such variations; however, since existing techniques have targeted Von-Neumann Architecture and nominal voltage circuits, it becomes nontrivial to apply them on near and subthreshold voltage accelerators, many of which do not base on the Von-Neumann Architecture. In particular, those accelerators often have no instruction, making it difficult to use the popular instruction-replay-based error correction. To tackle this challenge, in this paper, we propose a novel in situ EDAC technique that utilizes dynamic, temporarily, and spatially fine-grained body swapping for error correction without instruction replay. Using the proposed technique, we prototyped a spiking neural network (SNN) sorter in non-Von-Neumann Architecture. The prototyped chip can successfully remove the worst-case margin and, thus, achieve 49.3% higher energy efficiency and 35.6% higher throughput compared to the baseline that operates with the worst-case margin. The proposed technique incurs only 4.1% silicon area overhead and requires no additional supply voltage.
Yogesh Singh Chauhan - One of the best experts on this subject based on the ideXlab platform.
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neuromorphic circuits on fdsoi technology for computer vision applications
International Conference on VLSI Design, 2019Co-Authors: Dinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh ChauhanAbstract:Potential of neuromorphic circuits on FDSOI technology for computer vision applications is demonstrated in this paper. Computer vision systems based on conventional Von Neumann Architecture consume large area and energy. The FDSOI inverter-based circuits proposed in this work, require only 11 transistors per pixel for colour detection, and only 59 transistors per pixel for erosion and dilation operations, whereas the CMOS-based Boolean circuit requires more than 300 transistors per pixel, and 2700 transistors per pixel, respectively, for these operations.
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VLSI Design - Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications
2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), 2019Co-Authors: Dinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh ChauhanAbstract:Potential of neuromorphic circuits on FDSOI technology for computer vision applications is demonstrated in this paper. Computer vision systems based on conventional Von Neumann Architecture consume large area and energy. The FDSOI inverter-based circuits proposed in this work, require only 11 transistors per pixel for colour detection, and only 59 transistors per pixel for erosion and dilation operations, whereas the CMOS-based Boolean circuit requires more than 300 transistors per pixel, and 2700 transistors per pixel, respectively, for these operations.
Hoi-jun Yoo - One of the best experts on this subject based on the ideXlab platform.
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The Heterogeneous Deep Neural Network Processor With a Non-Von Neumann Architecture
Proceedings of the IEEE, 2020Co-Authors: Dongjoo Shin, Hoi-jun YooAbstract:Today’s CPUs are general-purpose processors, which have the Von Neumann Architecture (including the Harvard Architectures) to maximize the generality and programmability. On the other hand, application-specific integrated circuits (ASICs) have domain-specific Architectures to optimize the cost-effective performance but show very low generality. The combination of generality and ASIC, which usually seemed to have no contact, is expected to be enabled by deep learning (DL). DL, realized with deep neural networks (DNNs), has changed the paradigm of machine learning (ML) and brought significant progress in vision, speech, language processing, and many other applications. DNNs have special features that can be efficiently implemented with dedicated Architectures, ASICs. Sharing their special features, DNNs have a wide variety of network Architectures, and even the same network Architecture can be used for different applications depending on the weight parameters. This paper aims to provide the necessity, validity, and characteristics of the ML-specific integrated circuits (MSICs) that have a different Architecture from the Von Neumann Architecture. MSICs can avoid the overhead from the complex instruction set, instruction decoder, multilevel caches, and branch prediction of the recent Von Neumann Architecture processors designed for high generality and programmability. We will also discuss the necessity and validity of a heterogeneous Architecture in MSIC, starting from the differences between the visual-type information processing and the vector-type information processing, and show the chip implementation results.
