The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Zhihua Wang - One of the best experts on this subject based on the ideXlab platform.
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7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2014Co-Authors: Cong Shi, Zhongxiang Cao, Qi Qin, Nan-jian Wu, Ye Han, Jie Yang, Liyuan Liu, Zhihua WangAbstract:A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the Von Neumann Bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.
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ISSCC - 7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network
IEEE Journal of Solid-State Circuits, 2014Co-Authors: Cong Shi, Zhongxiang Cao, Qi Qin, Ye Han, Jie Yang, Liyuan Liu, Zhihua WangAbstract:A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the Von Neumann Bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.
Surya Jammalamadaka - One of the best experts on this subject based on the ideXlab platform.
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Graphene oxide based synaptic memristor device for neuromorphic computing.
Nanotechnology, 2021Co-Authors: Dwipak Prasad Sahu, Prabana Jetty, Surya JammalamadakaAbstract:Brain-inspired neuromorphic computing which consist neurons and synapses, with an ability to perform complex information processing has unfolded a new paradigm of computing to overcome the Von Neumann Bottleneck. Electronic synaptic memristor devices which can compete with the biological synapses are indeed significant for neuromorphic computing. In this work, we demonstrate our efforts to develop and realize the graphene oxide (GO) based memristor device as a synaptic device, which mimic as a biological synapse. Indeed, this device exhibits the essential synaptic learning behavior including analog memory characteristics, potentiation and depression. Furthermore, spike-timing-dependent-plasticity learning rule is mimicked by engineering the pre- and post-synaptic spikes. In addition, non-volatile properties such as endurance, retentivity, multilevel switching of the device are explored. These results suggest that Ag/GO/fluorine-doped tin oxide memristor device would indeed be a potential candidate for future neuromorphic computing applications.
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Graphene oxide based synaptic memristor device for neuromorphic computing.
Nanotechnology, 2021Co-Authors: Dwipak Prasad Sahu, Prabana Jetty, Surya JammalamadakaAbstract:Brain-inspired neuromorphic computing which consist neurons and synapses, with an ability to perform complex information processing has unfolded a new paradigm of computing to overcome the Von Neumann Bottleneck. Electronic synaptic memristor devices which can compete with the biological synapses are indeed significant for neuromorphic computing. In this work, we demonstrate our efforts to develop and realize the graphene oxide (GO) based memristor device as a synaptic device, which mimic as a biological synapse. Indeed, this device exhibits the essential synaptic learning behavior including analog memory characteristics, potentiation and depression. Furthermore, spike-timing-dependent-plasticity learning rule is mimicked by engineering the pre- and post-synaptic spikes. In addition, non-volatile properties such as endurance, retentivity, multilevel switching of the device are explored. These results suggest that Ag/GO/FTO memristor device would indeed be a potential candidate for future neuromorphic computing applications.
Jens Gustedt - One of the best experts on this subject based on the ideXlab platform.
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Memory Management for Union-Find Algorithms
1997Co-Authors: Christophe Fiorio, Jens GustedtAbstract:We provide a general tool to improve the real time performance of a broad class of Union-Find algorithms. This is done by minimizing the random access memory that is used and thus to avoid the well-known Von Neumann Bottleneck of synchronizing CPU and memory. A main application to image segmentation algorithms is demonstrated where the real time performance is drastically improved.
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STACS - Memory Management for Union-Find Algorithms
Lecture Notes in Computer Science, 1997Co-Authors: Christophe Fiorio, Jens GustedtAbstract:We provide a general tool to improve the real time performance of a broad class of Union-Find algorithms. This is done by minimizing the random access memory that is used and thus to avoid the well-known Von Neumann Bottleneck of synchronizing CPU and memory. A main application to image segmentation algorithms is demonstrated where the real time performance is drastically improved.
Cong Shi - One of the best experts on this subject based on the ideXlab platform.
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7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2014Co-Authors: Cong Shi, Zhongxiang Cao, Qi Qin, Nan-jian Wu, Ye Han, Jie Yang, Liyuan Liu, Zhihua WangAbstract:A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the Von Neumann Bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.
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ISSCC - 7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network
IEEE Journal of Solid-State Circuits, 2014Co-Authors: Cong Shi, Zhongxiang Cao, Qi Qin, Ye Han, Jie Yang, Liyuan Liu, Zhihua WangAbstract:A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the Von Neumann Bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.
Ye Zhou - One of the best experts on this subject based on the ideXlab platform.
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MXenes for memristive and tactile sensory systems
Applied Physics Reviews, 2021Co-Authors: Guanglong Ding, Kui Zhou, Baidong Yang, Su-ting Han, Ruo-si Chen, Ye ZhouAbstract:One of the most effective approaches to solving the current problem arising from the Von Neumann Bottleneck in this period of data proliferation is the development of intelligent devices that mimic the human learning process. Information sensing and processing/storage are considered to be the essential processes of learning. Therefore, high-performance sensors, memory/synaptic devices, and relevant intelligent artificial tactile perception systems are urgently needed. In this regard, innovative device concepts and emerging two-dimensional materials have recently received considerable attention. Herein, we discuss the development of MXenes for applications in tactile sensors, memristors, and artificial tactile perception systems. First, we summarize the structures, common properties, and synthesis and assembly techniques of MXenes. We then discuss the applications of MXenes in tactile sensors, memristors, and relevant neuromorphic-based artificial tactile perception systems along with the related working mechanisms. Finally, we present the challenges and prospects related to MXene synthesis, assembly, and application.
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One-dimensional materials for photoelectroactive memories and synaptic devices
Photo-Electroactive Nonvolatile Memories for Data Storage and Neuromorphic Computing, 2020Co-Authors: Guanglong Ding, Kui Zhou, Baidong Yang, Ye ZhouAbstract:Abstract The development of information age increases the demand of high-performance data storage and processing devices. Affected by Von Neumann Bottleneck and the failing of Moore’s law, photoelectroactive memory and brain-like data processing devices have been vigorously developed. Various one-dimensional (1D) materials have been applied for developing high-performance memories and synaptic devices. Herein, the application of 1D materials such as transition-metal oxide (TMO) nanowires, polymer nanowires, carbon nanotubes (CNTs), in both two and three terminal memories, and synaptic devices, especially in photoelectroactive devices, are reviewed. Moreover, the common synthetic methods of 1D materials and the device fabrication approaches are briefly reviewed.
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Artificial synapse emulated by charge tapping-based resistive switching device
'Wiley', 2019Co-Authors: Zhang Shi-rui, Li Zhou, Mao Jing-yu, Yi Ren, Yang Jia-qin, Yang Guang-hu, Zhu Xin, Han Su-ting, Roy, Vellaisamy A.l., Ye ZhouAbstract:The traditional Von Neumann architecture‐based computers are considered to be inadequate in the coming artificial intelligence era due to increasing computation complexity and rising power consumption. Neuromorphic computing may be the key role to emulate the human brain functions and eliminate the Von Neumann Bottleneck. As a basic unit in the nervous system, a synapse is responsible for transmitting information between neurons. Resistive random access memory (RRAM) is able to imitate the synaptic functions because of its tunable resistive switching behavior. Here, an artificial synapse based on solution processed polyvinylpyrrolidone (PVPy)–Au nanoparticle (NP) hybrid is fabricated, various synaptic functions including paired‐pulse facilitation (PPF), posttetanic potentiation (PTP), transformation from short‐term plasticity (STP) to long‐term plasticity (LTP) and learning‐forgetting‐relearning process are emulated, making the polymer–metal NPs hybrid system valuable candidates for the design of novel artificial neural architectures
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Infrared-Sensitive Memory Based on Direct-Grown MoS2 -Upconversion-Nanoparticle Heterostructure.
Advanced materials (Deerfield Beach Fla.), 2018Co-Authors: Yongbiao Zhai, Guanglong Ding, Ye Zhou, Yan Wang, Xueqing Yang, Feng Wang, Zhifan Qiu, Su-ting HanAbstract:Photonic memories as an emerging optoelectronic technology have attracted tremendous attention in the past few years due to their great potential to overcome the Von Neumann Bottleneck and to improve the performance of serial computers. Nowadays, the decryption technology for visible light is mature in photonic memories. Nevertheless, near-infrared (NIR) photonic memristors are less progressed. Herein, an NIR photonic memristor based on MoS2 -NaYF4 :Yb3+ , Er3+ upconversion nanoparticles (UCNPs) nanocomposites is designed. Under excitation by 980 nm NIR light, the UCNPs show emissions well overlapping with the absorption band of the MoS2 nanosheets. The heterostructure between the MoS2 and the UCNPs acting as excitons generation/separation centers remarkably improves the NIR-light-controlled memristor performance. Furthermore, in situ conductive atomic force microscopy is employed to elucidate the photo-modulated memristor mechanism. This work provides novel opportunities for NIR photonic memory that holds promise in future multifunctional robotics and electronic eyes.
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Photonic Synapses Based on Inorganic Perovskite Quantum Dots for Neuromorphic Computing.
Advanced materials (Deerfield Beach Fla.), 2018Co-Authors: Yan Wang, Ye Zhou, Jinrui Chen, Zhanpeng Wang, Li Zhou, Xiaoli Chen, Su-ting HanAbstract:Inspired by the biological neuromorphic system, which exhibits a high degree of connectivity to process huge amounts of information, photonic memory is expected to pave a way to overcome the Von Neumann Bottleneck for nonconventional computing. Here, a photonic flash memory based on all-inorganic CsPbBr3 perovskite quantum dots (QDs) is demonstrated. The heterostructure formed between the CsPbBr3 QDs and semiconductor layer serves as a basis for optically programmable and electrically erasable characteristics of the memory device. Furthermore, synapse functions including short-term plasticity, long-term plasticity, and spike-rate-dependent plasticity are emulated at the device level. The photonic potentiation and electrical habituation are implemented and the synaptic weight exhibits multiple wavelength response from 365, 450, 520 to 660 nm. These results may locate the stage for further thrilling novel advances in perovskite-based memories.
