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Meryem Marzouki – One of the best experts on this subject based on the ideXlab platform.

  • CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
    Journal of Electronic Testing, 2002
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression Mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

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  • Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism
    , 2001
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM’s architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

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  • CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
    , 2000
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    This paper describes CAS-BUS, a P1500 compatible test Access Mechanism for systems on a chip. The TAM architecture is made up of a core Access switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.

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Mounir Benabdenbi – One of the best experts on this subject based on the ideXlab platform.

  • STESOC: A Software-Based Test-AccessMechanism Controller
    , 2006
    Co-Authors: Matthieu Tuna, Mounir Benabdenbi, Alain Greiner

    Abstract:

    Software-based test of SoCs consists in testing IP cores using embedded processor cores. Previously proposed solutions are usually ad-hoc. Therefore, this paper presents STESOC, a software-based Test Access Mechanism for SoCs containing standard-wrapped IP cores. Under the control of the embedded microprocessor, a dedicated test-coprocessor tests the remaining components. Using the ITC02 SoC benchmarks a comparison is done between the STESOC architecture and a classical bus-based strategy.

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  • CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
    Journal of Electronic Testing, 2002
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression Mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

    Free Register to Access Article

  • Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism
    , 2001
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM’s architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

    Free Register to Access Article

Walid Maroufi – One of the best experts on this subject based on the ideXlab platform.

  • CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
    Journal of Electronic Testing, 2002
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression Mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

    Free Register to Access Article

  • Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism
    , 2001
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM’s architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

    Free Register to Access Article

  • CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
    , 2000
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

    Abstract:

    This paper describes CAS-BUS, a P1500 compatible test Access Mechanism for systems on a chip. The TAM architecture is made up of a core Access switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.

    Free Register to Access Article