Access Mechanism

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Meryem Marzouki - One of the best experts on this subject based on the ideXlab platform.

  • CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
    Journal of Electronic Testing, 2002
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression Mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

  • Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism
    2001
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

  • CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
    2000
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes CAS-BUS, a P1500 compatible test Access Mechanism for systems on a chip. The TAM architecture is made up of a core Access switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.

  • DATE - Testing TAPed cores and wrapped cores with the same test Access Mechanism
    Proceedings Design Automation and Test in Europe. Conference and Exhibition 2001, 1
    Co-Authors: M. Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

Mounir Benabdenbi - One of the best experts on this subject based on the ideXlab platform.

  • STESOC: A Software-Based Test-Access-Mechanism Controller
    2006
    Co-Authors: Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
    Abstract:

    Software-based test of SoCs consists in testing IP cores using embedded processor cores. Previously proposed solutions are usually ad-hoc. Therefore, this paper presents STESOC, a software-based Test Access Mechanism for SoCs containing standard-wrapped IP cores. Under the control of the embedded microprocessor, a dedicated test-coprocessor tests the remaining components. Using the ITC02 SoC benchmarks a comparison is done between the STESOC architecture and a classical bus-based strategy.

  • CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
    Journal of Electronic Testing, 2002
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression Mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

  • Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism
    2001
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

  • CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
    2000
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes CAS-BUS, a P1500 compatible test Access Mechanism for systems on a chip. The TAM architecture is made up of a core Access switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.

Walid Maroufi - One of the best experts on this subject based on the ideXlab platform.

  • CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
    Journal of Electronic Testing, 2002
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression Mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

  • Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism
    2001
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

  • CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
    2000
    Co-Authors: Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes CAS-BUS, a P1500 compatible test Access Mechanism for systems on a chip. The TAM architecture is made up of a core Access switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.

  • DATE - Testing TAPed cores and wrapped cores with the same test Access Mechanism
    Proceedings Design Automation and Test in Europe. Conference and Exhibition 2001, 1
    Co-Authors: M. Benabdenbi, Walid Maroufi, Meryem Marzouki
    Abstract:

    This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

C Papachristou - One of the best experts on this subject based on the ideXlab platform.

Erik Jan Marinissen - One of the best experts on this subject based on the ideXlab platform.

  • Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
    Journal of Electronic Testing, 2010
    Co-Authors: Ardy Berg, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens
    Abstract:

    Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or Network on Chip (NOC), can be reused as TAM; this will reduce the overall design effort and associated silicon area. For a given core, its test set, and maximal bandwidth that the functional interconnect can offer between test equipment and core-under-test, our approach instantiates a test wrapper for the core-under-test such that the test length is minimized. Unfortunately, it is unavoidable that along with the test data also unused (idle) bits are transported. This paper presents a holistic TAM bandwidth under-utilization analysis when functional interconnect is considered for test data transportation. We classify the idle bits into four types that refer to the root-cause of bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits.

  • Test Access Mechanism Optimization Test Scheduling, and Tester Data Volume Reduction for System-on-Chip
    IEEE Transactions on Computers, 2003
    Co-Authors: Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Abstract:

    We describe an integrated framework for system-on-chip (SOC) test automation. Our framework is based on a new test Access Mechanism (TAM) architecture consisting of flexible-width test buses that can fork and merge between cores. Test wrapper and TAM cooptimization for this architecture is performed by representing core tests using rectangles and by employing a novel rectangle packing algorithm for test scheduling. Test scheduling is tightly integrated with TAM optimization and it incorporates precedence and power constraints in the test schedule, while allowing the SOC integrator to designate a group of tests as preemptable. Test preemption helps avoid hardware and power consumption conflicts, thereby leading to a more efficient test schedule. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC. We present experimental results on our test automation framework for four benchmark SOCs.