The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
A Baschirotto - One of the best experts on this subject based on the ideXlab platform.
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a 0 9 v 3rd order single opamp Analog Filter in 28 nm bulk cmos
Analog Integrated Circuits and Signal Processing, 2019Co-Authors: S Damico, Marcello De Matteis, A Donno, A BaschirottoAbstract:This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass Filter based on an improved Active-gm-RC stage. Challenges related to the design of Analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The Filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed Filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art.
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a 28nm cmos 100mhz 1mw 12dbm iip3 4 th order flipped source follower Analog Filter
European Solid-State Circuits Conference, 2018Co-Authors: Federico Fary, M De Matteis, T Vergine, A BaschirottoAbstract:This paper presents the design in 28nm-CMOS technology of a 100MHz–3dB-bandwidth Analog Filter based on the Flipped-Source-Follower stage. The Filter performs large inband linearity thanks to a proper local loop, whose optimization at design level can be shielded from the Source-Follower input transistor that dominates the noise power. This enables better noise/linearity trade-off vs. power efficiency comparing with the Source-Follower Filters state-of-the-art. The circuit implements a 4th-order Butterworth low-pass transfer function and achieves 12.5dBm IIP3 at 968µW power consumption from a single 1V supply voltage. The in-band noise power spectral density is 8nV/√Hz resulting in an in-band integrated noise of 98µVRMS. Total Harmonic Distortion at 20 MHz is −40dB with −6dBm single tone output signal, resulting in 64dB Dynamic Range. The achieved Figure-of-Merit (160.5 J−1) compares very favorably with the state-of-the-art.
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a 0 9v 3rd order single opamp Analog Filter in 28nm cmos bulk
IEEE International Workshop on Advances in Sensors and Interfaces, 2017Co-Authors: Marcello De Matteis, S Damico, A Donno, Stefano Marinaci, A BaschirottoAbstract:A 3rd-order 132MHz cut-off frequency low-pass Filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of Analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The Filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order Filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μ\ν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.
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a 0 9v 75mhz 2 8mw 4th order Analog Filter in cmos bulk 28nm technology
International Symposium on Circuits and Systems, 2017Co-Authors: F Ciciotti, M De Matteis, A BaschirottoAbstract:In this paper a 75MHz 4th order low-pass Analog Filter in CMOS-28nm is presented. The Filter is composed by the cascade of two Active-RC Rauch biquadratic cells. The hereby proposed design manages a very low Vdd/Vth ratio (<2) for Standard-Process (SP) MOS transistors by means of a dedicated input Common-Mode (CM) feedback circuit (I-CMFB), that operates the OPAMP input differential pair in weak inversion region independently on common mode variations. The single Rauch cell exploits a feed-forward compensated OPAMP, where an improved output CM feedback (O-CMFB) circuit has been adopted reducing this way the parasitic poles of the CM loop, and improving O-CMFB phase margin. The OPAMP has been designed using a folded topology for stable operating point. The design prototype achieves 75MHz–3dB frequency at 2.8mW power consumption from a single 0.9V supply voltage, including also I-CMFB and O-CMFB power. In-band integrated noise is 320uVrms. The Filter performs 20dBm and 13dBm IIP3 at 6&11MHz and 50&55&MHz, respectively. Thanks to the very large linearity achieved at edge of the signal pass-band this design has one of the highest Figure-of-Merit for Active-RC Filters.
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a 63 db dr 22 5 mhz 21 5 dbm iip3 fourth order flfb Analog Filter
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Marcello De Matteis, F Resta, S Damico, A. Pipino, A. Pezzotta, A BaschirottoAbstract:In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) Filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active- RC /Active- $g_{m}$ - RC cells. The 0.18- $\mu \text{m}$ CMOS prototype performs 22.5-MHz −3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87- $\mu \text{V}_{\mathrm {RMS}}$ input referred iB integrated noise. The SNR for a −40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB $\cdot ~\text{J}^{-1})$ , which favourably compares to the state-of-the-art active- RC Analog Filters.
Marcello De Matteis - One of the best experts on this subject based on the ideXlab platform.
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a 0 9 v 3rd order single opamp Analog Filter in 28 nm bulk cmos
Analog Integrated Circuits and Signal Processing, 2019Co-Authors: S Damico, Marcello De Matteis, A Donno, A BaschirottoAbstract:This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass Filter based on an improved Active-gm-RC stage. Challenges related to the design of Analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The Filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed Filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art.
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continuous time Analog Filter with passband constant iip3 based on common gate amplifier
Analog Integrated Circuits and Signal Processing, 2017Co-Authors: Marcello De MatteisAbstract:This paper presents an Analog Filter based on Rauch biquadratic cell. The Filter exploits an improved Analog stage that makes linearity performance uniform over the entire pass-band frequency region. All feedback Analog Filters suffer from poor linearity when the input tones frequency is in close proximity to the closed-loop poles frequency, where loop-gain reduces. This often forces an overdesign with higher current (higher power consumption) and/or higher overdrive voltages (lower dynamic range) in order to meet the linearity specifications over the whole Filter pass-band region. The hereby proposed Rauch scheme resolves such a binding issue without power increasing and having the same IIP3 at low and at high frequency (up to the Filter closed-loop poles frequency). Hence the linearity performance is in first approximation independent on the input tones bandwidth. In order to validate the hereby proposed idea a 4th-order 25 MHz −3 dB bandwidth pseudo-differential Filter has been designed and simulated in CMOS 28 nm technology. The prototype consumes 820 µW from 1 V supply voltage and has 15 and 13 dBm IIP3 at 5 and 6 and 20 and 21 MHz input tones, respectively.
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a 0 9v 3rd order single opamp Analog Filter in 28nm cmos bulk
IEEE International Workshop on Advances in Sensors and Interfaces, 2017Co-Authors: Marcello De Matteis, S Damico, A Donno, Stefano Marinaci, A BaschirottoAbstract:A 3rd-order 132MHz cut-off frequency low-pass Filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of Analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The Filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order Filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μ\ν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.
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a 63 db dr 22 5 mhz 21 5 dbm iip3 fourth order flfb Analog Filter
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Marcello De Matteis, F Resta, S Damico, A. Pipino, A. Pezzotta, A BaschirottoAbstract:In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) Filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active- RC /Active- $g_{m}$ - RC cells. The 0.18- $\mu \text{m}$ CMOS prototype performs 22.5-MHz −3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87- $\mu \text{V}_{\mathrm {RMS}}$ input referred iB integrated noise. The SNR for a −40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB $\cdot ~\text{J}^{-1})$ , which favourably compares to the state-of-the-art active- RC Analog Filters.
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a 150mhz 3rd order single opamp continuous time Analog Filter in 28nm cmos technology
International Conference on Electronics Circuits and Systems, 2015Co-Authors: A Donno, S Damico, Marcello De Matteis, A BaschirottoAbstract:An improved Active-Gm-RC Filter architecture is proposed in this paper. With respect to the biquad Active-Gm-RC cell, this architecture exploits the second pole of the Opamp to increase the Filter order up to 3, while maintaining single Opamp topology. This reduces the required power per pole. A prototype of the low-pass Filter has been designed in 28nm CMOS technology. The Filter power consumption is 340μW with a 0.9V voltage supply, cut-off frequency is 150MHz achieving a Figure-of-Merit of 165dB.
S Damico - One of the best experts on this subject based on the ideXlab platform.
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a 0 9 v 3rd order single opamp Analog Filter in 28 nm bulk cmos
Analog Integrated Circuits and Signal Processing, 2019Co-Authors: S Damico, Marcello De Matteis, A Donno, A BaschirottoAbstract:This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass Filter based on an improved Active-gm-RC stage. Challenges related to the design of Analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The Filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed Filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art.
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a 0 9v 3rd order single opamp Analog Filter in 28nm cmos bulk
IEEE International Workshop on Advances in Sensors and Interfaces, 2017Co-Authors: Marcello De Matteis, S Damico, A Donno, Stefano Marinaci, A BaschirottoAbstract:A 3rd-order 132MHz cut-off frequency low-pass Filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of Analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The Filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order Filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μ\ν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.
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a 63 db dr 22 5 mhz 21 5 dbm iip3 fourth order flfb Analog Filter
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Marcello De Matteis, F Resta, S Damico, A. Pipino, A. Pezzotta, A BaschirottoAbstract:In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) Filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active- RC /Active- $g_{m}$ - RC cells. The 0.18- $\mu \text{m}$ CMOS prototype performs 22.5-MHz −3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87- $\mu \text{V}_{\mathrm {RMS}}$ input referred iB integrated noise. The SNR for a −40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB $\cdot ~\text{J}^{-1})$ , which favourably compares to the state-of-the-art active- RC Analog Filters.
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a 28 8mhz 21 1dbm iip3 3 2mw sallen key 4th order Filter with out of band zeros cancellation
International Symposium on Circuits and Systems, 2016Co-Authors: M De Matteis, F Resta, S Damico, A. Pipino, A BaschirottoAbstract:A 4th-order 28.8MHz low-pass Analog Filter uses a modified version of Sallen-Key (SK) biquad that solves the standard SK cell critical aspect due to the out-of-band zeros (OoB). The proposed cell completely cancel the OoB zeros by means of a low-power auxiliary path and a specific design optimization.
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a 150mhz 3rd order single opamp continuous time Analog Filter in 28nm cmos technology
International Conference on Electronics Circuits and Systems, 2015Co-Authors: A Donno, S Damico, Marcello De Matteis, A BaschirottoAbstract:An improved Active-Gm-RC Filter architecture is proposed in this paper. With respect to the biquad Active-Gm-RC cell, this architecture exploits the second pole of the Opamp to increase the Filter order up to 3, while maintaining single Opamp topology. This reduces the required power per pole. A prototype of the low-pass Filter has been designed in 28nm CMOS technology. The Filter power consumption is 340μW with a 0.9V voltage supply, cut-off frequency is 150MHz achieving a Figure-of-Merit of 165dB.
A A Abidi - One of the best experts on this subject based on the ideXlab platform.
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adaptive Analog if signal processor for a wide band cmos wireless receiver
IEEE Journal of Solid-state Circuits, 2001Co-Authors: F Behbahani, A Karimisanjaani, Weeguan Tan, A Roithmeier, J Leete, K Hoshino, A A AbidiAbstract:An IF strip for a wireless receiver supports a variable baud rate by changing Analog Filter bandwidth. Sliding and step adaptive dynamic range are both used at IF to dissipate only the necessary power at prevailing channel conditions. A combination of VGA and PGA is developed for 64-QAM. The total signal processor draws an average of 16 mA from 3.3 V and a peak of 73 mA. The differential input noise is as low as 3.9 nV//spl radic/Hz, while maximum IIP3 is +22 dBm with respect to 100 ohms.
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a broad band tunable cmos channel select Filter for a low if wireless receiver
Custom Integrated Circuits Conference, 1999Co-Authors: F Behbahani, A Karimisanjaani, Weeguan Tan, A Roithmeier, A A AbidiAbstract:Researchers agree that the active Filter for channel-selection limits the dynamic range in a fully integrated wireless receiver, which uses no external components. This paper describes a Filter designed for a wideband wireless LAN receiver operating in the 2.4-2.48 GHz ISM band. The receiver converts the desired channel to a low IF to enable on-chip rejection of the image. The Analog Filter must pass up to a 10 MHz wide single-channel centered after downconversion to IF ranging from 5 to 10 MHz. The classic requirements on all RF IC's apply to this Filter, namely how to achieve the desired frequency response with the highest linearity and lowest noise at a given current consumption. For a channel-select Filter, linearity is specified as out-of-band 3rd order intercept (IP3), to limit the in-band intermodulation from large interferers lying in the Filter stop band. This work addresses the problem in Filter architecture and circuit implementation. The achieved dynamic range surpasses all other published Filter designs, except those cases where gain is favorably interleaved with Filtering.
F Behbahani - One of the best experts on this subject based on the ideXlab platform.
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adaptive Analog if signal processor for a wide band cmos wireless receiver
IEEE Journal of Solid-state Circuits, 2001Co-Authors: F Behbahani, A Karimisanjaani, Weeguan Tan, A Roithmeier, J Leete, K Hoshino, A A AbidiAbstract:An IF strip for a wireless receiver supports a variable baud rate by changing Analog Filter bandwidth. Sliding and step adaptive dynamic range are both used at IF to dissipate only the necessary power at prevailing channel conditions. A combination of VGA and PGA is developed for 64-QAM. The total signal processor draws an average of 16 mA from 3.3 V and a peak of 73 mA. The differential input noise is as low as 3.9 nV//spl radic/Hz, while maximum IIP3 is +22 dBm with respect to 100 ohms.
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a broad band tunable cmos channel select Filter for a low if wireless receiver
Custom Integrated Circuits Conference, 1999Co-Authors: F Behbahani, A Karimisanjaani, Weeguan Tan, A Roithmeier, A A AbidiAbstract:Researchers agree that the active Filter for channel-selection limits the dynamic range in a fully integrated wireless receiver, which uses no external components. This paper describes a Filter designed for a wideband wireless LAN receiver operating in the 2.4-2.48 GHz ISM band. The receiver converts the desired channel to a low IF to enable on-chip rejection of the image. The Analog Filter must pass up to a 10 MHz wide single-channel centered after downconversion to IF ranging from 5 to 10 MHz. The classic requirements on all RF IC's apply to this Filter, namely how to achieve the desired frequency response with the highest linearity and lowest noise at a given current consumption. For a channel-select Filter, linearity is specified as out-of-band 3rd order intercept (IP3), to limit the in-band intermodulation from large interferers lying in the Filter stop band. This work addresses the problem in Filter architecture and circuit implementation. The achieved dynamic range surpasses all other published Filter designs, except those cases where gain is favorably interleaved with Filtering.