The Experts below are selected from a list of 213549 Experts worldwide ranked by ideXlab platform
C. Van Hoof - One of the best experts on this subject based on the ideXlab platform.
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flash analog to digital converter operational in an ultra wide temperature range room temperature to 4 2 k in standard cmos technology using a cryogenic reset switching scheme
Cryogenics, 2009Co-Authors: Ybe Creten, Patrick Merken, Robert Mertens, Willy Sansen, C. Van HoofAbstract:Abstract This work presents the design and test result of a standard 0.7 μm CMOS flash analog-to-digital converter (ADC) operational in an ultra wide temperature range (UWT, room temperature down to 4.2 K). To maintain the circuit’s performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated topology and switching schemes are utilized. Test results mentioned in this text are from a single process run, no design iterations were made.
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An 8-Bit Flash analog-to-digital converter in Standard CMOS Technology Functional From 4.2 K to 300 K
IEEE Journal of Solid-State Circuits, 2009Co-Authors: Ybe Creten, Patrick Merken, Robert Mertens, Willy Sansen, C. Van HoofAbstract:This paper presents the first flash analog-to-digital converter (ADC) in standard CMOS technology that functions from 300 K (room temperature) down to 4.2 K. It has been designed to operate in cryogenic sensor systems as they are cooled from room temperature to their final cryogenic operating temperature. In order to preserve the circuit's performance over this wide temperature range, even in the presence of temperature-induced transistor anomalies, dedicated architecture and switching schemes are employed. SPICE models for adequate circuit simulation at 4.2 K have been extracted. A first prototype of the chosen architecture, an 8-bit ADC in a standard 0.7 mum CMOS technology, achieves a differential nonlinearity (DNL) of 0.5 LSB at room temperature and 1 LSB at 4.2 K at a sampling frequency of 12.5 kHz.
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An 8-bit Flash analog-to-digital converter in standard CMOS technology functional in ultra wide temperature range from 4.2 K to 300 K
ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008Co-Authors: Ybe Creten, Patrick Merken, Robert Mertens, Willy Sansen, C. Van HoofAbstract:This paper presents the first standard CMOS flash analog-to-digital converter (ADC) operational over an ultra wide temperature range (UWT) from room temperature (27deg C or 300 K) down to 4 K (-269deg C). To preserve the circuits performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated architecture and switching schemes are employed.
S H Lewis - One of the best experts on this subject based on the ideXlab platform.
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a level crossing analog to digital converter with triangular dither
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Tunde Wang, Dong Wang, P J Hurst, Bernard C Levy, S H LewisAbstract:In this paper, a level-crossing analog-to-digital converter is described. It can convert audio bandwidth signals with high resolution using few threshold levels and digital interpolation. Samples are generated at nonuniform time intervals and then interpolated to produce uniformly spaced output samples. A periodic triangular dither signal added to the input ensures that low-amplitude or slowly varying signals are sampled and converted accurately. The dither is estimated and removed digitally before interpolation. Simulations show that greater than 10-bit resolution can be achieved with only seven comparators when using a sixth-order polynomial interpolator.
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a 12 bit 20 msample s pipelined analog to digital converter with nested digital background calibration
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Xiaoyue Wang, P J Hurst, S H LewisAbstract:A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.
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a 10b 120msample s time interleaved analog to digital converter with digital background calibration
International Solid-State Circuits Conference, 2002Co-Authors: S M Jamal, P J Hurs, S H LewisAbstract:Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.
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an 8 bit 80 msample s pipelined analog to digital converter with background calibration
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Jun Ming, S H LewisAbstract:An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm/sup 2/ in a single-poly 0.5 /spl mu/m CMOS technology.
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a 10 b 20 msample s analog to digital converter
IEEE Journal of Solid-state Circuits, 1992Co-Authors: S H Lewis, H S Fetterma, G Gross, R Ramachandra, T R ViswanathaAbstract:A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >
Huaijin Chen - One of the best experts on this subject based on the ideXlab platform.
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a 106 db snr hybrid oversampling analog to digital converter for digital audio
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Khiem Quang Nguyen, R Adams, Karl Sweetland, Huaijin ChenAbstract:An audio /spl Sigma//spl Delta/ analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-/spl mu/m CMOS process, and achieves 106-dB dynamic range, -99-dB THD+N.
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a 106 db snr hybrid oversampling analog to digital converter for digital audio
International Solid-State Circuits Conference, 2005Co-Authors: Khiem Quang Nguyen, R Adams, Karl Sweetland, Huaijin ChenAbstract:An audio ΣΔ analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-μm CMOS process, and achieves 106-dB dynamic range, -99-dB THD + N.
Bahram Jalali - One of the best experts on this subject based on the ideXlab platform.
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digital broadband linearization technique and its application to photonic time stretch analog to digital converter
Optics Letters, 2011Co-Authors: Ali Fard, Shalabh Gupta, Bahram JalaliAbstract:Suppression of distortion induced by nonlinearity in a dynamical system (such as an analog optical link) is very challenging, particularly for a wide-bandwidth signal. Conventional compensation techniques are computationally intensive, significantly limiting their realization in real-time applications. Here, we propose and demonstrate an efficient digital postprocessing technique to suppress distortions added to a wideband signal by a nonlinear system with memory effect. Experimentally, digital broadband linearization of the photonic time-stretch analog-to-digital converter (TSADC) is demonstrated. In case of TSADC, a dynamic range improvement of >15 dB compared to conventional memory-less correction method is achieved.
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time warp correction and calibration in photonic time stretch analog to digital converter
Optics Letters, 2008Co-Authors: Shalabh Gupta, Bahram JalaliAbstract:We show how time warps caused by nonuniform wavelength-to-time mapping in the photonic time-stretch analog-to-digital converter (ADC) can be digitally measured and removed. This is combined with digital correction of wavelength-dependent Mach-Zehnder modulator (MZM) bias offset to attain a 10 GHz bandwidth digitizer with >7 effective bits of resolution and 52 dB spur-free dynamic range. To the best of our knowledge, this is the highest resolution ADC in 10 GHz bandwidth range, with at least 1 order of magnitude higher signal-to-noise ratio than ever achieved. We also demonstrate concatenation of 30 wavelength interleaved time segments with high fidelity on the path to achieving continuous time operation.
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continuous time time stretched analog to digital converter array implemented using virtual time gating
IEEE Transactions on Circuits and Systems, 2005Co-Authors: Y Han, Bahram JalaliAbstract:We demonstrate the continuous-time operation of a time-stretch analog-to-digital converter array. A continuous-time RF signal is segmented into parallel channels and each channel is stretched in time prior to digitization. The technique offers improvement in the effective input bandwidth and sampling rate of the digitizer. The implementation uses virtual time gating for interleaving segments of the continuous-time RF signal. The signal is first modulated onto a linearly chirped optical carrier and then sliced, in time, using passive optical filters. This technique obviates the need for fast switching gates. It results in minimum interchannel mismatch and in hardware efficiency since all channels are stretched using the same electro-optic modulator and the same dispersive elements.
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130 gsa s photonic analog to digital converter with time stretch preprocessor
IEEE Photonics Technology Letters, 2002Co-Authors: A S Bhushan, Bahram Jalali, P V Kelkar, Ozdal Boyraz, M N IslamAbstract:In this letter, we demonstrate a photonic analog-to-digital converter with time stretch (TS) preprocessor that has a sampling rate of 130 GSa/s. The system has a signal-to-noise ratio (SNR) exceeding seven effective number of bits over a 1-GHz bandwidth at 18 GHz. We present an analytical model of the SNR in the TS preprocessor which shows that over the specified bandwidth, the SNR is limited by the amplified spontaneous emission beat noise.
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Optical folding-flash analog-to-digital converter with analog encoding.
Optics Letters, 1995Co-Authors: Bahram Jalali, Y. M. XieAbstract:We describe an optically assisted folding-flash analog-to-digital converter. The periodic transfer function of the Mach–Zehnder interferometer is used to perform analog folding on the electronic signal to be quantized. A novel analog encoding scheme for efficient generation of gray code digital data is proposed. The new encoding scheme eliminates the requirement for interferometers with ultralow Vπ, which, so far, has hindered the development of such systems. The encoding concept is experimentally demonstrated through the use of LiNbO3 modulators.
Ybe Creten - One of the best experts on this subject based on the ideXlab platform.
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flash analog to digital converter operational in an ultra wide temperature range room temperature to 4 2 k in standard cmos technology using a cryogenic reset switching scheme
Cryogenics, 2009Co-Authors: Ybe Creten, Patrick Merken, Robert Mertens, Willy Sansen, C. Van HoofAbstract:Abstract This work presents the design and test result of a standard 0.7 μm CMOS flash analog-to-digital converter (ADC) operational in an ultra wide temperature range (UWT, room temperature down to 4.2 K). To maintain the circuit’s performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated topology and switching schemes are utilized. Test results mentioned in this text are from a single process run, no design iterations were made.
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An 8-Bit Flash analog-to-digital converter in Standard CMOS Technology Functional From 4.2 K to 300 K
IEEE Journal of Solid-State Circuits, 2009Co-Authors: Ybe Creten, Patrick Merken, Robert Mertens, Willy Sansen, C. Van HoofAbstract:This paper presents the first flash analog-to-digital converter (ADC) in standard CMOS technology that functions from 300 K (room temperature) down to 4.2 K. It has been designed to operate in cryogenic sensor systems as they are cooled from room temperature to their final cryogenic operating temperature. In order to preserve the circuit's performance over this wide temperature range, even in the presence of temperature-induced transistor anomalies, dedicated architecture and switching schemes are employed. SPICE models for adequate circuit simulation at 4.2 K have been extracted. A first prototype of the chosen architecture, an 8-bit ADC in a standard 0.7 mum CMOS technology, achieves a differential nonlinearity (DNL) of 0.5 LSB at room temperature and 1 LSB at 4.2 K at a sampling frequency of 12.5 kHz.
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An 8-bit Flash analog-to-digital converter in standard CMOS technology functional in ultra wide temperature range from 4.2 K to 300 K
ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008Co-Authors: Ybe Creten, Patrick Merken, Robert Mertens, Willy Sansen, C. Van HoofAbstract:This paper presents the first standard CMOS flash analog-to-digital converter (ADC) operational over an ultra wide temperature range (UWT) from room temperature (27deg C or 300 K) down to 4 K (-269deg C). To preserve the circuits performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated architecture and switching schemes are employed.