The Experts below are selected from a list of 201 Experts worldwide ranked by ideXlab platform
Matthew Mattina - One of the best experts on this subject based on the ideXlab platform.
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tarantula a vector extension to the alpha architecture
International Symposium on Computer Architecture, 2002Co-Authors: Roger Espasa, Federico Ardanaz, Joel Emer, Stephen Felix, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Geoff Lowney, Matthew MattinaAbstract:Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6, 5]. Tarantula adds to the EV8 core a vector unit capable of 32 double-precision flops per cycle. The vector unit fetches data directly from a 16 MByte second level cache with a peak bandwidth of sixty four 64-bit values per cycle. The whole chip is backed by a memory controller capable of delivering over 64 GBytes/s of raw band- width. Tarantula extends the Alpha ISA with new vector instructions that operate on new Architectural State. Salient features of the architecture and implementation are: (1) it fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, (2) provides high bandwidth for non-unit stride memory accesses, (3) supports gather/scatter instructions efficiently, (4) fully integrates with the EV8 core with a narrow, streamlined interface, rather than acting as a co-processor, (5) can achieve a peak of 104 operations per cycle, and (6) achieves excellent "real-computation" per transistor and per watt ratios. Our detailed simulations show that Tarantula achieves an average speedup of 5X over EV8, out of a peak speedup in terms of flops of 8X. Furthermore, performance on gather/scatter intensive benchmarks such as Radix Sort is also remarkable: a speedup of almost 3X over EV8 and 15 sustained operations per cycle. Several benchmarks exceed 20 operations per cycle.
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ISCA - Tarantula: a vector extension to the alpha architecture
ACM SIGARCH Computer Architecture News, 2002Co-Authors: Roger Espasa, Federico Ardanaz, Joel Emer, Stephen Felix, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Geoff Lowney, Matthew MattinaAbstract:Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6, 5]. Tarantula adds to the EV8 core a vector unit capable of 32 double-precision flops per cycle. The vector unit fetches data directly from a 16 MByte second level cache with a peak bandwidth of sixty four 64-bit values per cycle. The whole chip is backed by a memory controller capable of delivering over 64 GBytes/s of raw band- width. Tarantula extends the Alpha ISA with new vector instructions that operate on new Architectural State. Salient features of the architecture and implementation are: (1) it fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, (2) provides high bandwidth for non-unit stride memory accesses, (3) supports gather/scatter instructions efficiently, (4) fully integrates with the EV8 core with a narrow, streamlined interface, rather than acting as a co-processor, (5) can achieve a peak of 104 operations per cycle, and (6) achieves excellent "real-computation" per transistor and per watt ratios. Our detailed simulations show that Tarantula achieves an average speedup of 5X over EV8, out of a peak speedup in terms of flops of 8X. Furthermore, performance on gather/scatter intensive benchmarks such as Radix Sort is also remarkable: a speedup of almost 3X over EV8 and 15 sustained operations per cycle. Several benchmarks exceed 20 operations per cycle.
Rolland Crunk - One of the best experts on this subject based on the ideXlab platform.
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HALSIM—a very fast SPARC V9 behavioral model
ACM SIGARCH Computer Architecture News, 1994Co-Authors: David Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal Saxena, Rolland CrunkAbstract:This paper describes several implementation techniques used in HAL's 250 KIPS SPARC V9 behavioral model. Beyond presenting the details of our processor model, we describe several areas of innovation: Architectural State-vector capture for injection into a gate-level hardware model, using an EDC polynomial-based signature scheme to verify a hardware design; obtaining accurate kernel and user-mode instruction trace data.
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MASCOTS - HALSIM-a very fast SPARC-V9 behavioral model
MASCOTS '95. Proceedings of the Third International Workshop on Modeling Analysis and Simulation of Computer and Telecommunication Systems, 1Co-Authors: David Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal Saxena, Rolland CrunkAbstract:This paper describes several implementation techniques used in HAL's 500 KIPS SPARC V9 behavioral model. Beyond presenting the details of our processor model, we describe several areas of innovation: Architectural State-vector capture for injection into a gate-level hardware model, using an EDC polynomial-based signature scheme to verify a hardware design; obtaining accurate kernel and user-mode instruction trace data. >
Magnus Själander - One of the best experts on this subject based on the ideXlab platform.
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ISCA - Efficient invisible speculative execution through selective delay and value prediction
Proceedings of the 46th International Symposium on Computer Architecture, 2019Co-Authors: Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus SjälanderAbstract:Speculative execution, the base on which modern high-performance general-purpose CPUs are built on, has recently been shown to enable a slew of security attacks. All these attacks are centered around a common set of behaviors: During speculative execution, the Architectural State of the system is kept unmodified, until the speculation can be verified. In the event that a misspeculation occurs, then anything that can affect the Architectural State is reverted (squashed) and re-executed correctly. However, the same is not true for the microArchitectural State. Normally invisible to the user, changes to the microArchitectural State can be observed through various side-channels, with timing differences caused by the memory hierarchy being one of the most common and easy to exploit. The speculative side-channels can then be exploited to perform attacks that can bypass software and hardware checks in order to leak information. These attacks, out of which the most infamous are perhaps Spectre and Meltdown, have led to a frantic search for solutions. In this work, we present our own solution for reducing the microArchitectural State-changes caused by speculative execution in the memory hierarchy. It is based on the observation that if we only allow accesses that hit in the L1 data cache to proceed, then we can easily hide any microArchitectural changes until after the speculation has been verified. At the same time, we propose to prevent stalls by value predicting the loads that miss in the L1. Value prediction, though speculative, constitutes an invisible form of speculation, not seen outside the core. We evaluate our solution and show that we can prevent observable microArchitectural changes in the memory hierarchy while keeping the performance and energy costs at 11% and 7%, respectively. In comparison, the current State of the art solution, InvisiSpec, incurs a 46% performance loss and a 51% energy increase.
Sai Ram Dheeraj Lokam - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - NEMESIS: a software approach for computing in presence of soft errors
2017 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2017Co-Authors: Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj LokamAbstract:Soft errors are considered as the main reliability challenge for sub-nanoscale microprocessors. Software-level soft error resilience schemes are desirable because they require no hardware modifications and their protection can be tuned based on the application requirements. However, existing software-level error tolerant schemes do not provide high-level of protection. In this work, we present NEMESIS - a compiler-level fine-grain soft error detection, diagnosis and recovery technique that can provide high degree of error-resiliency. NEMESIS runs three versions of computations and detects soft errors by checking the results of all memory write and branch operations. In the case of mismatch, NEMESIS recovery routine reverts the effect of error from the Architectural State of the program and program resumes its normal execution. Our extensive μ-Architectural-level fault injection experiments results show that NEMESIS transformation is able to detect all soft errors and recover from 97% of detected errors.
Lawrence T. Clark - One of the best experts on this subject based on the ideXlab platform.
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An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits
IEEE Transactions on Computers, 2016Co-Authors: Lawrence T. Clark, Dan W. Patterson, Chandarasekaran Ramamurthy, Keith E. HolbertAbstract:A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart—only matching results commit to Architectural State. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining Architectural State is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm2\mg LETEFF. We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.
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A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery
IEEE Transactions on Nuclear Science, 2016Co-Authors: Chad Farnsworth, Vinay Vashishtha, Lawrence T. Clark, Anudeep R. Gogulamudi, Aditya GujjaAbstract:A MIPS 4Kc compliant embedded microprocessor design that incorporates Architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-Architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to Architectural State. At this point, an exception is taken and software recovers the correct machine State and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.
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CICC - A soft-error hardened process portable embedded microprocessor
2015 IEEE Custom Integrated Circuits Conference (CICC), 2015Co-Authors: Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad FarnsworthAbstract:An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via Architectural, micro-Architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to Architectural State. Added instructions allow software controlled recovery and restart of upset instructions. Key Architectural State is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.
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Architectural and Micro-Architectural Techniques for Software Controlled Microprocessor Soft-Error Mitigation
2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2015Co-Authors: Anudeep R. Gogulamudi, Srivatsan Chellappa, Lawrence T. Clark, Chad Farnsworth, Vinay VashishthaAbstract:A MIPS 4Kc compliant embedded microprocessor core design that incorporates Architectural features for software controlled radiation upset recovery is presented. The design uses fault tolerance techniques, i.e., error detection and instruction restart, implemented at the micro-Architectural level, with Architectural level changes, i.e., new instructions, for error recovery. Fine-grained, self-correcting triple mode redundant circuits protect key Architectural State, in addition to dual mode redundancy in the instruction execution pipelines, cache subsystems, and error detection and correction in the register file. The design is implemented in a commercial low standby power 90-nm bulk low standby power CMOS process and the prototype operates at up to 336 MHz.
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A 90 nm Bulk CMOS Radiation Hardened by Design Cache Memory
IEEE Transactions on Nuclear Science, 2010Co-Authors: Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith E. HolbertAbstract:A RHBD high performance cache fabricated on 90 nm bulk CMOS is presented. Test silicon cache data arrays can read and write at 1.02 GHz. Irradiation to 2 Mrad(Si) negligibly impacts standby current. The cache is write-through, and relies on error checking to allow cache invalidation when single event upsets or potential single event transients are detected. The write-through cache Architectural State will then naturally be reloaded by the ensuing microprocessor operations. Single cycle invalidation is supported. Single event error ion beam test results are presented, as is a description of measured single event effects in array and peripheral circuits and their mitigation by the design.