Average Packet Latency - Explore the Science & Experts | ideXlab

Scan Science and Technology

Contact Leading Edge Experts & Companies

Average Packet Latency

The Experts below are selected from a list of 588 Experts worldwide ranked by ideXlab platform

Radu Marculescu – 1st expert on this subject based on the ideXlab platform

  • DATE – SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2013, 2013
    Co-Authors: Zhiliang Qian, Da-cheng Juan, Paul Bogdan, Chi-ying Tsui, Diana Marculescu, Radu Marculescu

    Abstract:

    In this work, we propose SVR-NoC, a learning-based support vector regression (SVR) model for evaluating Network-on-Chip (NoC) Latency performance. Different from the state-of-the-art NoC analytical model, which uses classical queuing theory to directly compute the Average channel waiting time, the proposed SVR-NoC model performs NoC Latency analysis based on learning the typical training data. More specifically, we develop a systematic machine-learning framework that uses the kernel-based support vector regression method to predict the channel Average waiting time and the traffic flow Latency. Experimental results show that SVR-NoC can predict the Average Packet Latency accurately while achieving about 120X speed-up over simulation-based evaluation methods.

  • “It’s a small world after all”: NoC performance optimization via long-range link insertion
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006
    Co-Authors: Umit Y. Ogras, Radu Marculescu

    Abstract:

    Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an archi- tecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few ap- plication-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the Average Packet Latency and a major improvement in the achievable network through with minimal impact on network topology.

  • ICCAD – Application-specific network-on-chip architecture customization via long-range link insertion
    ICCAD-2005. IEEE ACM International Conference on Computer-Aided Design 2005., 2005
    Co-Authors: Umit Y. Ogras, Radu Marculescu

    Abstract:

    Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the Average Packet Latency and a major improvement in the network achievable throughput.

Umit Y. Ogras – 2nd expert on this subject based on the ideXlab platform

  • “It’s a small world after all”: NoC performance optimization via long-range link insertion
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006
    Co-Authors: Umit Y. Ogras, Radu Marculescu

    Abstract:

    Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an archi- tecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few ap- plication-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the Average Packet Latency and a major improvement in the achievable network through with minimal impact on network topology.

  • ICCAD – Application-specific network-on-chip architecture customization via long-range link insertion
    ICCAD-2005. IEEE ACM International Conference on Computer-Aided Design 2005., 2005
    Co-Authors: Umit Y. Ogras, Radu Marculescu

    Abstract:

    Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the Average Packet Latency and a major improvement in the network achievable throughput.

  • Application-specific network-on-chip architecture customization via long-range link insertion
    IEEE ACM International Conference on Computer-Aided Design Digest of Technical Papers ICCAD, 2005
    Co-Authors: Umit Y. Ogras, Radu Marculescu

    Abstract:

    Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the Average Packet Latency and a major improvement in the network achievable throughput.

Axel Jantsch – 3rd expert on this subject based on the ideXlab platform

  • ASICON – Performance analysis of on-chip bufferless router with multi-ejection ports
    2015 IEEE 11th International Conference on ASIC (ASICON), 2015
    Co-Authors: Chaochao Feng, Zhonghai Lu, Axel Jantsch, Zhuofan Liao, Zhenyu Zhao

    Abstract:

    In general, the bufferless NoC router has only one local output port for ejection, which may lead to multiple arriving flits competing for the only one output port. In this paper, we propose a reconfigurable bufferless router in which the number of ejection ports can be configured as 2, 3 and 4. Simulation results demonstrate that the Average Packet Latency of the routers with multi-ejection ports is 18%, 10%, 6%, 14%, 9% and 7% on Average less than that of the router with 1 ejection ports under six synthetic workloads respectively. For application workloads, the Average Packet Latency of the router with more than two ejection ports is slightly better than the router with only one ejection port, which can be neglect. Making a compromise of hardware cost and performance, it can be concluded that it is no need to implement bufferless routers with 3 and 4 ejection ports, as the router with 2 ejection ports can achieve almost the same performance as the routers with 3 and 4 ejection ports.

  • A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs
    Routing Algorithms in Networks-on-Chip, 2013
    Co-Authors: Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu

    Abstract:

    In this chapter, we present a system-level framework for designing minimal deterministic routing algorithms for Networks-on-Chip (NoCs) that are customized for a set of applications. To this end, we first formulate an optimization problem of minimizing Average Packet Latency in the network and then use the simulated annealing heuristic to solve this problem. To estimate the Average Packet Latency we use a queueing-based analytical model which can capture the burstiness of the traffic. The proposed framework does not require virtual channels to guarantee deadlock freedom since routes are extracted from an acyclic channel dependency graph. Experiments with both synthetic and realistic workloads show the effectiveness of the approach. Results show that maximum sustainable throughput of the network is improved for different applications and architectures.

  • An Analytical Latency Model for Networks-on-Chip
    IEEE Transactions on Very Large Scale Integration Systems, 2013
    Co-Authors: Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch

    Abstract:

    We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed model takes as input an application communication graph, a topology graph, a mapping vector, and a routing matrix, and estimates Average Packet Latency and router blocking time. It works for arbitrary network topology with deterministic routing under arbitrary traffic patterns. This model can estimate per-flow Average Latency accurately and quickly, thus enabling fast design space exploration of various design parameters in NoC designs. Experimental results show that the proposed analytical model can predict the Average Packet Latency more than four orders of magnitude faster than an accurate simulation, while the computation error is less than 10% in non-saturated networks for different system-on-chip platforms.