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Sorin Cotofana - One of the best experts on this subject based on the ideXlab platform.

  • ASAP - Binary Multiplication based on single electron tunneling
    2004
    Co-Authors: C Lageweg, Sorin Cotofana, Stamatis Vassiliadis
    Abstract:

    This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.

  • Binary Multiplication based on single electron tunneling
    Application-Specific Systems Architectures and Processors, 2004
    Co-Authors: C Lageweg, Sorin Cotofana, Stamatis Vassiliadis
    Abstract:

    This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.

  • Threshold logic parallel counters for 32-bit multipliers
    Smart Structures Devices and Systems, 2002
    Co-Authors: Peter Celinski, Sorin Cotofana, Derek Abbott
    Abstract:

    In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for Binary Multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.

  • Serial Binary Multiplication with feed-forward neural networks
    Neurocomputing, 1999
    Co-Authors: Sorin Cotofana, Stamatis Vassiliadis
    Abstract:

    Abstract In this paper we propose no learning based neural networks for serial Binary Multiplication. We show that for “subarray-wise” generation of the partial product matrix and a data transmission rate of δ bits per cycle the serial Multiplication of two n bits operands can be computed in ⌈n/δ⌉ serial cycles with an O (nδ) size neural network, and maximum fan-in and weight values both in the order of O (δ log δ) . The minimum delay for this scheme is in the order of ⌈ n ⌉+ log n and it corresponds to a data transmission rate of ⌈ n ⌉ bits per cycle. For “column-wise” generation of the partial product matrix and a data transmission rate of 1-bit per cycle the serial Multiplication can be achieved in 2n−1+(k+1)⌈ log k n⌉ delay with a (k+1)(n−1)/(k−1) size neural network, a maximum weight of 2 k and a maximum fan-in of 3k+1 . If a data transmission rate of δ bits per serial cycle is assumed we prove a delay of ⌈(2n−1)/δ⌉+(δ+1)⌈ log n⌉ for a (δ+1)(n−1) size neural network, a maximum weight of 2 δ and a maximum fan-in of 3δ+1 .

  • ISCAS - Electron counting based high-radix Multiplication in single electron tunneling technology
    2006 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: Cor Meenderinck, Sorin Cotofana
    Abstract:

    This paper investigates the implementation of high-radix Multiplication based on the electron counting (EC) paradigm in single electron tunneling (SET) technology. First we propose a Multiplication scheme which conceptually speaking follows the structure of traditional full-tree multipliers. The high-radix EC Multiplication scheme comprises three steps and of each an implementation is presented. Second, an 8-bit radix 4 EC multiplier is designed and verified by means of simulation. The high-radix Multiplication scheme is evaluated in terms of area and delay for different operand sizes and compared with corresponding Binary Multiplication schemes in SET technology. Both type of implementations prove to have similar delay times, but the EC based scheme requires up to five times less area.

Stamatis Vassiliadis - One of the best experts on this subject based on the ideXlab platform.

  • ASAP - Binary Multiplication based on single electron tunneling
    2004
    Co-Authors: C Lageweg, Sorin Cotofana, Stamatis Vassiliadis
    Abstract:

    This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.

  • Binary Multiplication based on single electron tunneling
    Application-Specific Systems Architectures and Processors, 2004
    Co-Authors: C Lageweg, Sorin Cotofana, Stamatis Vassiliadis
    Abstract:

    This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.

  • Serial Binary Multiplication with feed-forward neural networks
    Neurocomputing, 1999
    Co-Authors: Sorin Cotofana, Stamatis Vassiliadis
    Abstract:

    Abstract In this paper we propose no learning based neural networks for serial Binary Multiplication. We show that for “subarray-wise” generation of the partial product matrix and a data transmission rate of δ bits per cycle the serial Multiplication of two n bits operands can be computed in ⌈n/δ⌉ serial cycles with an O (nδ) size neural network, and maximum fan-in and weight values both in the order of O (δ log δ) . The minimum delay for this scheme is in the order of ⌈ n ⌉+ log n and it corresponds to a data transmission rate of ⌈ n ⌉ bits per cycle. For “column-wise” generation of the partial product matrix and a data transmission rate of 1-bit per cycle the serial Multiplication can be achieved in 2n−1+(k+1)⌈ log k n⌉ delay with a (k+1)(n−1)/(k−1) size neural network, a maximum weight of 2 k and a maximum fan-in of 3k+1 . If a data transmission rate of δ bits per serial cycle is assumed we prove a delay of ⌈(2n−1)/δ⌉+(δ+1)⌈ log n⌉ for a (δ+1)(n−1) size neural network, a maximum weight of 2 δ and a maximum fan-in of 3δ+1 .

Cor Meenderinck - One of the best experts on this subject based on the ideXlab platform.

P. V. Srinivasa Rao - One of the best experts on this subject based on the ideXlab platform.

  • 2-Absorbing Primary Subsemimodules Over Partial Semirings
    The Journal of the Indian Mathematical Society, 2021
    Co-Authors: N. Ravi Babu, T. V. Pradeep Kumar, P. V. Srinivasa Rao
    Abstract:

    A partial semiring is a structure possessing an infinitary partial addition and a Binary Multiplication, subject to a set of axioms. The partial functions under disjoint-domain sums and functional compo- sition is a partial semiring. In this paper we obtain the characteristics of 2-absorbing primary subsemimodules and weakly 2-absorbing primary subsemimodules in partial semirings.

Masanori Kanazawa - One of the best experts on this subject based on the ideXlab platform.

  • FPL - The Fastest Multiplier on FPGAs with Redundant Binary Representation
    Lecture Notes in Computer Science, 2000
    Co-Authors: Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa
    Abstract:

    In this paper, we propose the fastest Binary Multiplication algorithm on 4-LUT FPGAs. Our key idea is k-bit compaction, in which the n-bit multiplier is divided into n/k digits in 2k -nary's, then the multiplicand is multiplied with each digit into a middle-product. And our second idea is oneminus-one encoding for the redundant Binary representation. We've compared 2-bit, 3-bit and 4-bit compactions. And we have been able to construct 16-bit and 24-bit Binary multipliers in 11 levels and 13 levels of 4-LUTs, respectively.