The Experts below are selected from a list of 3021 Experts worldwide ranked by ideXlab platform
John Keane - One of the best experts on this subject based on the ideXlab platform.
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5 6 mb mm 2 1r1w 8t sram arrays operating down to 560 mv utilizing small signal sensing with charge shared Bitline and asymmetric sense amplifier in 14 nm finfet cmos technology
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Jaydeep P Kulkarni, John Keane, Kyunghoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin ZhangAbstract:Multiported high-performance on-die memories occupy significantly more die area than a comparable single-port memory. Among various multiport memory topologies, the 1-read (R), 1-write (W) 8-transistor (T) Static Random Access Memory (SRAM) with a decoupled read port allows separate optimization of the read and write ports when organized without interleaved logical columns. This enables a lower minimum operating voltage ( $V_{\mathrm{ min}}$ ) compared with other dual-port SRAMs that require ports optimized for read stability and write operations. However, the 1R1W 8T SRAM often employs large signal, hierarchical Bitline sensing to achieve high performance due to the nondifferential read Bitline. This large-signal read architecture necessitates frequently placed local Bitline sensing circuits, degrading the array bit density. In this paper, we present two sense amplifier (SA) techniques for small-signal pseudo-differential sensing to facilitate 256 bits per Bitline achieving an 8T SRAM array density of 5.6 Mb/mm $^{2}\vphantom {^{\int ^\int }}$ in 14 nm FinFET CMOS. The first design employs a charge sharing SA scheme to generate a reference voltage ( $V_{\mathrm{ REF}}$ ) by leveraging the capacitance of otherwise unused metal tracks over the bitcell column. The second design utilizes an asymmetric SA in which the read Bitline precharged to $V_{\mathrm{ CC}}$ in the unselected sector acts as a reference voltage and the active Bitline side is intentionally upsized to skew the SA. High volume measurement results demonstrate 560 mV $V_{\min }$ at 400 MHz/−10 °C and reaches 2.21 GHz at 1 V supply.
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5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Jaydeep P Kulkarni, John Keane, Kyunghoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin ZhangAbstract:Multiported high-performance on-die memories occupy significantly more die area than a comparable single-port memory. Among various multiport memory topologies, the 1-read (R), 1-write (W) 8-transistor (T) Static Random Access Memory (SRAM) with a decoupled read port allows separate optimization of the read and write ports when organized without interleaved logical columns. This enables a lower minimum operating voltage ( $V_{\mathrm{ min}}$ ) compared with other dual-port SRAMs that require ports optimized for read stability and write operations. However, the 1R1W 8T SRAM often employs large signal, hierarchical Bitline sensing to achieve high performance due to the nondifferential read Bitline. This large-signal read architecture necessitates frequently placed local Bitline sensing circuits, degrading the array bit density. In this paper, we present two sense amplifier (SA) techniques for small-signal pseudo-differential sensing to facilitate 256 bits per Bitline achieving an 8T SRAM array density of 5.6 Mb/mm $^{2}\vphantom {^{\int ^\int }}$ in 14 nm FinFET CMOS. The first design employs a charge sharing SA scheme to generate a reference voltage ( $V_{\mathrm{ REF}}$ ) by leveraging the capacitance of otherwise unused metal tracks over the bitcell column. The second design utilizes an asymmetric SA in which the read Bitline precharged to $V_{\mathrm{ CC}}$ in the unselected sector acts as a reference voltage and the active Bitline side is intentionally upsized to skew the SA. High volume measurement results demonstrate 560 mV $V_{\min }$ at 400 MHz/−10 °C and reaches 2.21 GHz at 1 V supply.
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18.5 A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme
2014Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:Robust high-density subthreshold SRAMs are indispensable for emerging ultra-low power applications such as implantable devices, medical instruments, and wireless sensor networks. Conventional 6T SRAMs in the subthreshold region fail to deliv-er the density and yield requirements due to the reduced static noise margin (SNM), poor writability, limited number of cells per Bitline, and reduced Bitline sensing margin. 8T and 10T SRAM cells have been proposed to improve the SNM by decoupling the SRAM cell nodes from the Bitline and hence making the read mode SNM equal to the hold mode SNM [1,2]. This paper intro-duces various circuit techniques for designing robust high-densi-ty subthreshold SRAMs: (i) decoupled cell for read margin improvement, (ii) utilizing reverse short channel effect (RSCE) for write margin improvement, (iii) eliminating data-dependent Bitline leakage to enable long Bitlines, (iv) virtual ground replic
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A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
IEEE Journal of Solid-State Circuits, 2008Co-Authors: Tae-hyoung Kim, John Keane, J. Liu, Chris H. KimAbstract:A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per Bitline by eliminating the data-dependent Bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A Bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.
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a high density subthreshold sram with data independent Bitline leakage and virtual ground replica scheme
International Solid-State Circuits Conference, 2007Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:A 10T SRAM cell with data-independent Bitline leakage and a virtual-ground replica scheme allows 1k cells per Bitline in subthreshold SRAMs. Reverse short-channel effect is used to improve writability, offer higher speed, reduce junction capacitance, and decrease circuit variability. A 0.13mum, the 480kb SRAM test chip shows a minimum operating voltage of 0.20V.
Chris H. Kim - One of the best experts on this subject based on the ideXlab platform.
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18.5 A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme
2014Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:Robust high-density subthreshold SRAMs are indispensable for emerging ultra-low power applications such as implantable devices, medical instruments, and wireless sensor networks. Conventional 6T SRAMs in the subthreshold region fail to deliv-er the density and yield requirements due to the reduced static noise margin (SNM), poor writability, limited number of cells per Bitline, and reduced Bitline sensing margin. 8T and 10T SRAM cells have been proposed to improve the SNM by decoupling the SRAM cell nodes from the Bitline and hence making the read mode SNM equal to the hold mode SNM [1,2]. This paper intro-duces various circuit techniques for designing robust high-densi-ty subthreshold SRAMs: (i) decoupled cell for read margin improvement, (ii) utilizing reverse short channel effect (RSCE) for write margin improvement, (iii) eliminating data-dependent Bitline leakage to enable long Bitlines, (iv) virtual ground replic
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A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
IEEE Journal of Solid-State Circuits, 2008Co-Authors: Tae-hyoung Kim, John Keane, J. Liu, Chris H. KimAbstract:A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per Bitline by eliminating the data-dependent Bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A Bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.
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a high density subthreshold sram with data independent Bitline leakage and virtual ground replica scheme
International Solid-State Circuits Conference, 2007Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:A 10T SRAM cell with data-independent Bitline leakage and a virtual-ground replica scheme allows 1k cells per Bitline in subthreshold SRAMs. Reverse short-channel effect is used to improve writability, offer higher speed, reduce junction capacitance, and decrease circuit variability. A 0.13mum, the 480kb SRAM test chip shows a minimum operating voltage of 0.20V.
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ISSCC - A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:A 10T SRAM cell with data-independent Bitline leakage and a virtual-ground replica scheme allows 1k cells per Bitline in subthreshold SRAMs. Reverse short-channel effect is used to improve writability, offer higher speed, reduce junction capacitance, and decrease circuit variability. A 0.13mum, the 480kb SRAM test chip shows a minimum operating voltage of 0.20V.
Tony Tae-hyoung Kim - One of the best experts on this subject based on the ideXlab platform.
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read Bitline sensing and fast local write back techniques in hierarchical Bitline architecture for ultralow voltage srams
IEEE Transactions on Very Large Scale Integration Systems, 2016Co-Authors: Bo Wang, Tony Tae-hyoung KimAbstract:Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read Bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized Bitline scheme to eliminate the leakage dependence on data pattern and thus improves RBL sensing and its resilience against process, voltage, and temperature variations. In addition, we propose a fast local write-back (WB) technique to implement a half-select-free write operation. With hierarchical Bitline architecture, it facilitates a local read and a subsequent fast WB action to secure the original data without performance degradation. A 16-kb SRAM test chip has been fabricated in a 65-nm CMOS technology and achieved the minimum operating voltage of 0.24 V with a read access time of 4.88 $\mu \text{s}$ .
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design of an ultra low voltage 9t sram with equalized Bitline leakage and cam assisted energy efficiency improvement
IEEE Transactions on Circuits and Systems, 2015Co-Authors: Bo Wang, Truc Quynh Nguyen, Jun Zhou, Tony Tae-hyoung KimAbstract:This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized Bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read Bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on Bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 $\mu {\rm s}$ . Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V $\sim$ 0.6 V by the proposed CAM-assisted circuit.
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A low voltage 8-T SRAM with PVT-tracking Bitline sensing margin enhancement for high operating temperature (up to 300°C)
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013Co-Authors: Tony Tae-hyoung KimAbstract:An 8-Kbit low power 8-T SRAM for high temperature (up to 300°C) applications is presented. Near-threshold operation is selected for minimum performance variations over a wide temperate range. We proposed a PVT-tracking Bitline sensing margin enhancement technique to improve the Bitline swing and the sensing window. Test chips fabricated in a commercial 1.0-μm SOI technology with high temperature interconnection option demonstrates successful SRAM operation at 2 V, 300°C. The power consumption and access time of 0.94 mW and 256ns was achieved at 2 V and 300°C.
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A 0.2V 16Kb 9T SRAM with Bitline leakage equalization and CAM-assisted write performance boosting for improving energy efficiency
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012Co-Authors: Bo Wang, Anh Tuan, Truc Quynh Nguyen, Jun Zhou, Tony Tae-hyoung KimAbstract:An energy efficient 9T SRAM with Bitline leakage equalization and Content-Addressable-Memory-assisted (CAM-assisted) performance boosting techniques is presented. The equalized read Bitline leakage improves the read Bitline swing by 6.8× at 0.2V. The proposed CAM-assisted boosting technique enhances the write performance of the multi-threshold CMOS (MTCMOS) SRAM array implemented with higher-Vth (HVT) devices. The inserted tiny CAM conceals the slow data development after data flipping, and therefore improves overall operating frequency in the near threshold region. A 16Kb SRAM test chip was fabricated in 65nm CMOS technology and showed the minimum energy of 0.33 pJ at 0.4V.
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ESSDERC - A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized Bitlines and fast local write-back for cell stability improvement
2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012Co-Authors: Bo Wang, Tony Tae-hyoung KimAbstract:A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized Bitline scheme is proposed to improve both read Bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V.
Tae-hyoung Kim - One of the best experts on this subject based on the ideXlab platform.
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18.5 A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme
2014Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:Robust high-density subthreshold SRAMs are indispensable for emerging ultra-low power applications such as implantable devices, medical instruments, and wireless sensor networks. Conventional 6T SRAMs in the subthreshold region fail to deliv-er the density and yield requirements due to the reduced static noise margin (SNM), poor writability, limited number of cells per Bitline, and reduced Bitline sensing margin. 8T and 10T SRAM cells have been proposed to improve the SNM by decoupling the SRAM cell nodes from the Bitline and hence making the read mode SNM equal to the hold mode SNM [1,2]. This paper intro-duces various circuit techniques for designing robust high-densi-ty subthreshold SRAMs: (i) decoupled cell for read margin improvement, (ii) utilizing reverse short channel effect (RSCE) for write margin improvement, (iii) eliminating data-dependent Bitline leakage to enable long Bitlines, (iv) virtual ground replic
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A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
IEEE Journal of Solid-State Circuits, 2008Co-Authors: Tae-hyoung Kim, John Keane, J. Liu, Chris H. KimAbstract:A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per Bitline by eliminating the data-dependent Bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A Bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.
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a high density subthreshold sram with data independent Bitline leakage and virtual ground replica scheme
International Solid-State Circuits Conference, 2007Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:A 10T SRAM cell with data-independent Bitline leakage and a virtual-ground replica scheme allows 1k cells per Bitline in subthreshold SRAMs. Reverse short-channel effect is used to improve writability, offer higher speed, reduce junction capacitance, and decrease circuit variability. A 0.13mum, the 480kb SRAM test chip shows a minimum operating voltage of 0.20V.
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ISSCC - A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007Co-Authors: Tae-hyoung Kim, Jason Liu, John Keane, Chris H. KimAbstract:A 10T SRAM cell with data-independent Bitline leakage and a virtual-ground replica scheme allows 1k cells per Bitline in subthreshold SRAMs. Reverse short-channel effect is used to improve writability, offer higher speed, reduce junction capacitance, and decrease circuit variability. A 0.13mum, the 480kb SRAM test chip shows a minimum operating voltage of 0.20V.
Onur Mutlu - One of the best experts on this subject based on the ideXlab platform.
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Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost
ACM Transactions on Architecture and Code Optimization, 2016Co-Authors: Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Samira Khan, Onur MutluAbstract:3D-stacked DRAM alleviates the limited memory bandwidth bottleneck that exists in modern systems by leveraging through silicon vias (TSVs) to deliver higher external memory channel bandwidth. Today’s systems, however, cannot fully utilize the higher bandwidth offered by TSVs, due to the limited internal bandwidth within each layer of the 3D-stacked DRAM. We identify that the bottleneck to enabling higher bandwidth in 3D-stacked DRAM is now the global Bitline interface, the connection between the DRAM row buffer and the peripheral IO circuits. The global Bitline interface consists of a limited and expensive set of wires and structures, called global Bitlines and global sense amplifiers, whose high cost makes it difficult to simply scale up the bandwidth of the interface within a single DRAM layer in the 3D stack. We alleviate this bandwidth bottleneck by exploiting the observation that several global Bitline interfaces already exist across the multiple DRAM layers in current 3D-stacked designs, but only a fraction of them are enabled at the same time. We propose a new 3D-stacked DRAM architecture, called Simultaneous Multi-Layer Access (SMLA), which increases the internal DRAM bandwidth by accessing multiple DRAM layers concurrently, thus making much greater use of the bandwidth that the TSVs offer. To avoid channel contention, the DRAM layers must coordinate with each other when simultaneously transferring data. We propose two approaches to coordination, both of which deliver four times the bandwidth for a four-layer DRAM, over a baseline that accesses only one layer at a time. Our first approach, Dedicated-IO, statically partitions the TSVs by assigning each layer to a dedicated set of TSVs that operate at a higher frequency. Unfortunately, Dedicated-IO requires a nonuniform design for each layer (increasing manufacturing costs), and its DRAM energy consumption scales linearly with the number of layers. Our second approach, Cascaded-IO, solves both issues by instead time multiplexing all of the TSVs across layers. Cascaded-IO reduces DRAM energy consumption by lowering the operating frequency of higher layers. Our evaluations show that SMLA provides significant performance improvement and energy reduction across a variety of workloads (55p/18p on average for multiprogrammed workloads, respectively) over a baseline 3D-stacked DRAM, with low overhead.
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Tiered-latency DRAM: A low latency and low cost DRAM architecture
Proceedings - International Symposium on High-Performance Computer Architecture, 2013Co-Authors: Donghyuk Lee, Yoongu Kim, Jamie Liu, Lavanya Subramanian, V. Seshadri, Onur MutluAbstract:The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today's systems. We observe that the high access latency is not intrinsic to DRAM, but a trade-off made to decrease cost-per-bit. To mitigate the high area overhead of DRAM sensing structures, commodity DRAMs connect many DRAM cells to each sense-amplifier through a wire called a Bitline. These Bitlines have a high parasitic capacitance due to their long length, and this Bitline capacitance is the dominant source of DRAM latency. Specialized low-latency DRAMs use shorter Bitlines with fewer cells, but have a higher cost-per-bit due to greater sense-amplifier area overhead. In this work, we introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each long Bitline is split into two shorter segments by an isolation transistor, allowing one segment to be accessed with the latency of a short-Bitline DRAM without incurring high cost-per-bit. We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache. Evaluations show that our proposed mechanisms improve both performance and energy-efficiency for both single-core and multi-programmed workloads.