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Hai Q. Chiang - One of the best experts on this subject based on the ideXlab platform.

  • thin film transistors with transparent amorphous zinc indium tin oxide Channel Layer
    Journal of Physics D, 2007
    Co-Authors: M S Grover, Hai Q. Chiang, John F. Wager, Peter A Hersh, E S Kettenring, Douglas A Keszler
    Abstract:

    Thin-film transistors (TFTs) with transparent amorphous zinc indium tin oxide (ZITO) Channel Layer are demonstrated. Optical transmission of the Channel Layer is approximately 85% in the visible portion of the electromagnetic spectrum. The Channel Layer is formed via rf magnetron sputter deposition and then furnace annealed in air. Peak incremental mobilities of 5–19 cm2 V−1 s−1 and turn-on voltages of −4 to −17 V are obtained for devices annealed post-deposition at 100–300 °C, respectively. Current–voltage measurements indicate n-Channel, depletion-mode transistor operation with excellent drain current saturation and a drain current on-to-off ratio greater than 106. ZITO is one example of an emerging class of high performance TFT Channel materials involving transparent amorphous multicomponent oxides composed of heavy-metal cations with (n − 1)d10ns0 (n ≥ 4) electronic configuration.

  • zinc tin oxide thin film transistors via reactive sputtering using a metal target
    Journal of Vacuum Science & Technology B, 2006
    Co-Authors: David Hong, Hai Q. Chiang, John F. Wager
    Abstract:

    Zinc tin oxide based thin-film transistors are fabricated via reactive magnetron sputtering using a metallic zinc/tin alloy target. The oxygen partial pressure and total sputtering pressure are explored. An oxygen partial pressure and total sputtering pressure of 0.8 and 30mTorr, respectively, are found to be optimal. Devices with a reactively sputtered zinc tin oxide Channel Layer and Channel Layer annealing of 500°C exhibit incremental mobilities of ∼32cm2V−1s−1, turn-on voltage of ∼−4V and drain current on-to-off ratios of ∼107. Both direct current and radio frequency magnetron sputtering are explored showing similar characteristics.

  • transparent thin film transistors with zinc indium oxide Channel Layer
    Journal of Applied Physics, 2005
    Co-Authors: Nicole L Dehuff, Hai Q. Chiang, David Hong, John F. Wager, E S Kettenring, Randy Hoffman, Cheolhee Park, Douglas A Keszler
    Abstract:

    High mobility, n-type transparent thin-film transistors (TTFTs) with a zinc indium oxide (ZIO) Channel Layer are reported. Such devices are highly transparent with ∼85% optical transmission in the visible portion of the electromagnetic spectrum. ZIO TTFTs annealed at 600 °C operate in depletion-mode with threshold voltages −20 to −10V and turn-on voltages ∼3V less than the threshold voltage. These devices have excellent drain current saturation, peak incremental Channel mobilities of 45–55cm2V−1s−1, drain current on-to-off ratios of ∼106, and inverse subthreshold slopes of ∼0.8V∕decade. In contrast, ZIO TTFTs annealed at 300 °C typically operate in enhancement-mode with threshold voltages of 0–10V and turn-on voltages 1–2V less than the threshold voltage. These 300 °C devices exhibit excellent drain–current saturation, peak incremental Channel mobilities of 10–30cm2V−1s−1, drain current on-to-off ratios of ∼106, and inverse subthreshold slopes of ∼0.3V∕decade. ZIO TTFTs with the Channel Layer deposited ne...

  • High mobility transparent thin-film transistors with amorphous zinc tin oxide Channel Layer
    Applied Physics Letters, 2005
    Co-Authors: Hai Q. Chiang, R. L. Hoffman, J. Jeong, John F. Wager, Douglas A Keszler
    Abstract:

    Transparent thin-film transistors(TTFTs) with an amorphous zinc tin oxide Channel Layer formed via rf magnetron sputter deposition are demonstrated. Field-effect mobilities of 5–15 and 20 – 50 cm 2 V − 1 s − 1 are obtained for devices post-deposition annealed at 300 and 600 ° C , respectively. TTFTs processed at 300 and 600 ° C yield devices with turn-on voltage of 0–15 and − 5 – 5 V , respectively. Under both processing conditions, a drain current on-to-off ratio greater than 10 7 is obtained. Zinc tin oxide is one example of a new class of high performance TTFT Channel materials involving amorphous oxides composed of heavy-metal cations with ( n − 1 ) d 10 ns 0 ( n ⩾ 4 ) electronic configurations.

Jae Kyeong Jeong - One of the best experts on this subject based on the ideXlab platform.

Douglas A Keszler - One of the best experts on this subject based on the ideXlab platform.

  • thin film transistors with transparent amorphous zinc indium tin oxide Channel Layer
    Journal of Physics D, 2007
    Co-Authors: M S Grover, Hai Q. Chiang, John F. Wager, Peter A Hersh, E S Kettenring, Douglas A Keszler
    Abstract:

    Thin-film transistors (TFTs) with transparent amorphous zinc indium tin oxide (ZITO) Channel Layer are demonstrated. Optical transmission of the Channel Layer is approximately 85% in the visible portion of the electromagnetic spectrum. The Channel Layer is formed via rf magnetron sputter deposition and then furnace annealed in air. Peak incremental mobilities of 5–19 cm2 V−1 s−1 and turn-on voltages of −4 to −17 V are obtained for devices annealed post-deposition at 100–300 °C, respectively. Current–voltage measurements indicate n-Channel, depletion-mode transistor operation with excellent drain current saturation and a drain current on-to-off ratio greater than 106. ZITO is one example of an emerging class of high performance TFT Channel materials involving transparent amorphous multicomponent oxides composed of heavy-metal cations with (n − 1)d10ns0 (n ≥ 4) electronic configuration.

  • transparent thin film transistors with zinc indium oxide Channel Layer
    Journal of Applied Physics, 2005
    Co-Authors: Nicole L Dehuff, Hai Q. Chiang, David Hong, John F. Wager, E S Kettenring, Randy Hoffman, Cheolhee Park, Douglas A Keszler
    Abstract:

    High mobility, n-type transparent thin-film transistors (TTFTs) with a zinc indium oxide (ZIO) Channel Layer are reported. Such devices are highly transparent with ∼85% optical transmission in the visible portion of the electromagnetic spectrum. ZIO TTFTs annealed at 600 °C operate in depletion-mode with threshold voltages −20 to −10V and turn-on voltages ∼3V less than the threshold voltage. These devices have excellent drain current saturation, peak incremental Channel mobilities of 45–55cm2V−1s−1, drain current on-to-off ratios of ∼106, and inverse subthreshold slopes of ∼0.8V∕decade. In contrast, ZIO TTFTs annealed at 300 °C typically operate in enhancement-mode with threshold voltages of 0–10V and turn-on voltages 1–2V less than the threshold voltage. These 300 °C devices exhibit excellent drain–current saturation, peak incremental Channel mobilities of 10–30cm2V−1s−1, drain current on-to-off ratios of ∼106, and inverse subthreshold slopes of ∼0.3V∕decade. ZIO TTFTs with the Channel Layer deposited ne...

  • High mobility transparent thin-film transistors with amorphous zinc tin oxide Channel Layer
    Applied Physics Letters, 2005
    Co-Authors: Hai Q. Chiang, R. L. Hoffman, J. Jeong, John F. Wager, Douglas A Keszler
    Abstract:

    Transparent thin-film transistors(TTFTs) with an amorphous zinc tin oxide Channel Layer formed via rf magnetron sputter deposition are demonstrated. Field-effect mobilities of 5–15 and 20 – 50 cm 2 V − 1 s − 1 are obtained for devices post-deposition annealed at 300 and 600 ° C , respectively. TTFTs processed at 300 and 600 ° C yield devices with turn-on voltage of 0–15 and − 5 – 5 V , respectively. Under both processing conditions, a drain current on-to-off ratio greater than 10 7 is obtained. Zinc tin oxide is one example of a new class of high performance TTFT Channel materials involving amorphous oxides composed of heavy-metal cations with ( n − 1 ) d 10 ns 0 ( n ⩾ 4 ) electronic configurations.

  • tin oxide transparent thin film transistors
    Journal of Physics D, 2004
    Co-Authors: Rick E Presley, David Hong, John F. Wager, Cheolhee Park, C L Munsee, Douglas A Keszler
    Abstract:

    A SnO2 transparent thin-film transistor (TTFT) is demonstrated. The SnO2 Channel Layer is deposited by RF magnetron sputtering and then rapid thermal annealed in O2 at 600°C. The TTFT is highly transparent, and enhancement-mode behaviour is achieved by employing a very thin Channel Layer (10–20 nm). Maximum field-effect mobilities of 0.8 cm2 V−1 s−1 and 2.0 cm2 V−1 s−1 are obtained for enhancement- and depletion-mode devices, respectively. The transparent nature and the large drain current on-to-off ratio of 105 associated with the enhancement-mode behaviour of these devices may prove useful for novel gas-sensor applications.

Y W Heo - One of the best experts on this subject based on the ideXlab platform.

  • effects of ambient atmosphere on the transfer characteristics and gate bias stress stability of amorphous indium gallium zinc oxide thin film transistors
    Applied Physics Letters, 2010
    Co-Authors: Sangyun Sung, Jun Hyuk Choi, Un Bin Han, Ki Chang Lee, Joonhyung Lee, Jeongjoo Kim, Wantae Lim, S J Pearton, D P Norton, Y W Heo
    Abstract:

    We investigated the transfer characteristics and the gate-bias stability of amorphous indium-gallium-zinc oxide thin-film transistors when the Channel Layer was exposed to hydrogen, oxygen, air, or vacuum at room temperature during measurements. The threshold voltage and the drain current were changed by the ambient atmospheres. The threshold voltage shift (ΔVth) under gate-bias stress was faster in hydrogen than in oxygen and vacuum. It is suggested that hydrogen exposure degrades the gate-bias stress stability due to surface accumulation Layer creation. The characteristic trapping times, τ, in H2, O2, air, and vacuum were 5×103, 1.5×104, 2×104, and 6.3×104 s, respectively.

  • transparent amorphous indium zinc oxide thin film transistors fabricated at room temperature
    Applied Physics Letters, 2007
    Co-Authors: Juil Song, Joonhyung Lee, Jeongjoo Kim, Y W Heo, Jaesoung Park, Howoon Kim, Gyeongeup Kim, Byeong Dae Choi
    Abstract:

    The authors report on transparent thin-film transistors using amorphous indium zinc oxides for an active Channel Layer and gate-source-drain electrodes fabricated by rf magnetron sputtering at room temperature. The conducting properties of the amorphous indium zinc oxides were controlled by oxygen partial pressures in the sputtering ambient. An amorphous AlOx served as the gate dielectric oxide. Devices were realized that display a threshold voltage of 1.1V and an on/off ratio of ∼106 operated as a n-type enhancement mode with saturation mobility of 0.53cm2∕Vs. The devices showed optical transmittance about 80% in the visible range.

  • progress in semiconducting oxide based thin film transistors for displays
    Semiconductor Science and Technology, 2005
    Co-Authors: Y W Kwon, D P Norton, Y W Heo, M Jones, J Zhou, Shyhchyang Luo, Paul H Holloway, Elliot P Douglas, Z V Park
    Abstract:

    Recent progress in the development of transparent thin-film transistors for integration with flexible displays is discussed. Specifically, the fabrication and properties of ZnO-based thin-film transistors on glass are described. Top-gate-type thin-film transistors with transparent n-type ZnO as the active Channel Layer have been fabricated via wet photolithography processing. The ZnO Layers were deposited using pulsed laser deposition. A low leakage current of 10−7 A cm−2 was realized with amorphous HfO2 or (Ce, Tb)MgA11O19 as the gate dielectric. N-Channel depletion-mode operation was shown for the undoped ZnO thin-film transistors. Phosphorus-doped ZnO and (Zn, Mg)O were also utilized as Channel materials in order to realize a reduction in carrier density. The current–voltage measurements demonstrate an enhancement-mode device operation for the thin-film transistors with P-doped (Zn, Mg)O as the active Channel Layer and HfO2 serving as the gate dielectric.

Shinichi Takagi - One of the best experts on this subject based on the ideXlab platform.

  • source engineering for biLayer tunnel field effect transistor with hetero tunnel junction thickness and impurity concentration
    Applied Physics Express, 2020
    Co-Authors: Kimihiko Kato, Mitsuru Takenaka, Takahiro Mori, Yukinori Morita, Takashi Matsukawa, Shinichi Takagi
    Abstract:

    We have investigated impacts of a source Layer thickness, a source impurity concentration and a Channel thickness in a biLayer tunneling field-effect transistor (TFET) with a thin-film hetero tunneling junction on the electrical characteristics. Device simulation has revealed that thinning of the source Layer significantly degrades on-state current (I on) due to non-uniform band-to-band tunneling over the tunneling junction, while the Channel Layer thinning is effective to increase Ion. On the other hand, the source/Channel impurity concentrations of around 3×1018 cm‒3 are found to be optimal for high I on, I on/I off and suppression of transfer characteristics shift with changing V d.

  • biLayer tunneling field effect transistor with oxide semiconductor and group iv semiconductor hetero junction simulation analysis of electrical characteristics
    AIP Advances, 2019
    Co-Authors: Kimihiko Kato, Hitoshi Tabata, Hiroaki Matsui, Mitsuru Takenaka, Shinichi Takagi
    Abstract:

    Operation mechanisms and electrical characteristics of tunneling field-effect transistors (TFETs) employing a hetero tunneling junction by utilizing an n-type oxide-semiconductor (OS) and a p-type group-IV-semiconductor are comprehensibly analyzed. Gate-normal band-to-band tunneling (BTBT) has high potential for the superior TFET performance such as high on-state current and small sub-threshold swing (S.S.). Additionally, a hetero tunneling junction with type-II energy band alignment is promising to exponentially increase tunneling probability with keeping small off-state current. Therefore, in this study, we investigate the impact of key material and device parameters such as energy band alignment of source/Channel regions and thickness of the OS Channel Layer or gate insulator based on technology computer aided design (TCAD) simulation. The gate-controlled uniform band bending along the source-drain direction realizes uniform BTBT in the entire region of the hetero tunneling junction. Also, the reduction of the tunneling barrier height, which is continuously controlled by the conduction band minimum of the OS-Channel and the valence band maximum of the IV-source, is effective to increases on-state current and decrease S.S. value. On the other hand, the thicknesses of OS Channel Layer and gate insulator have strong influences on tunneling probability and threshold voltage. Therefore, the sub-threshold characteristics of TFETs are sensitive to non-uniformities in the tunneling junction such as Channel thickness fluctuation and surface potential fluctuation at the metal-oxide-semiconductor (MOS) interfaces. These numerical analyses of the device operation are essentially important to understand the effects of key device parameters on the TFET performance and to realize the superior electrical performance.

  • biLayer tunneling field effect transistor with oxide semiconductor and group iv semiconductor hetero junction simulation analysis of electrical characteristics
    AIP Advances, 2019
    Co-Authors: Kimihiko Kato, Hitoshi Tabata, Hiroaki Matsui, Mitsuru Takenaka, Shinichi Takagi
    Abstract:

    Operation mechanisms and electrical characteristics of tunneling field-effect transistors (TFETs) employing a hetero tunneling junction by utilizing an n-type oxide-semiconductor (OS) and a p-type group-IV-semiconductor are comprehensibly analyzed. Gate-normal band-to-band tunneling (BTBT) has high potential for the superior TFET performance such as high on-state current and small sub-threshold swing (S.S.). Additionally, a hetero tunneling junction with type-II energy band alignment is promising to exponentially increase tunneling probability with keeping small off-state current. Therefore, in this study, we investigate the impact of key material and device parameters such as energy band alignment of source/Channel regions and thickness of the OS Channel Layer or gate insulator based on technology computer aided design (TCAD) simulation. The gate-controlled uniform band bending along the source-drain direction realizes uniform BTBT in the entire region of the hetero tunneling junction. Also, the reduction of the tunneling barrier height, which is continuously controlled by the conduction band minimum of the OS-Channel and the valence band maximum of the IV-source, is effective to increases on-state current and decrease S.S. value. On the other hand, the thicknesses of OS Channel Layer and gate insulator have strong influences on tunneling probability and threshold voltage. Therefore, the sub-threshold characteristics of TFETs are sensitive to non-uniformities in the tunneling junction such as Channel thickness fluctuation and surface potential fluctuation at the metal-oxide-semiconductor (MOS) interfaces. These numerical analyses of the device operation are essentially important to understand the effects of key device parameters on the TFET performance and to realize the superior electrical performance.Operation mechanisms and electrical characteristics of tunneling field-effect transistors (TFETs) employing a hetero tunneling junction by utilizing an n-type oxide-semiconductor (OS) and a p-type group-IV-semiconductor are comprehensibly analyzed. Gate-normal band-to-band tunneling (BTBT) has high potential for the superior TFET performance such as high on-state current and small sub-threshold swing (S.S.). Additionally, a hetero tunneling junction with type-II energy band alignment is promising to exponentially increase tunneling probability with keeping small off-state current. Therefore, in this study, we investigate the impact of key material and device parameters such as energy band alignment of source/Channel regions and thickness of the OS Channel Layer or gate insulator based on technology computer aided design (TCAD) simulation. The gate-controlled uniform band bending along the source-drain direction realizes uniform BTBT in the entire region of the hetero tunneling junction. Also, the reductio...

  • tin al2o3 zno gate stack engineering for top gate thin film transistors by combination of post oxidation and annealing
    Applied Physics Letters, 2018
    Co-Authors: Kimihiko Kato, Hitoshi Tabata, Hiroaki Matsui, Mitsuru Takenaka, Shinichi Takagi
    Abstract:

    Control of fabrication processes for a gate stack structure with a ZnO thin Channel Layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO Layer are defective just after the Al2O3 Layer formation by atomic Layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and Channel Layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO Layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.Control of fabrication processes for a gate stack structure with a ZnO thin Channel Layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO Layer are defective just after the Al2O3 Layer formation by atomic Layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and Channel Layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO Layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increas...