The Experts below are selected from a list of 90501 Experts worldwide ranked by ideXlab platform
Henning Sirringhaus - One of the best experts on this subject based on the ideXlab platform.
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low temperature high performance solution Processed metal oxide thin film transistors formed by a sol gel on Chip Process
Nature Materials, 2011Co-Authors: Kulbinder K Banger, Yoshihisa Yamashita, Kiyotaka Mori, Rebecca L Peterson, Timothy J Leedham, J Rickard, Henning SirringhausAbstract:A low-temperature, solution-based preparation of amorphous, metal oxide semiconducting thin-films is reported. This ‘sol–gel on Chip’ hydrolysis approach yields thin-film transistors with high field-effect mobilities, reproducible and stable turn-on voltages and high operational stability.
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Low-temperature, high-performance solution-Processed metal oxide thin-film transistors formed by a ‘sol–gel on Chip’ Process
Nature Materials, 2011Co-Authors: Kulbinder K Banger, Yoshihisa Yamashita, Kiyotaka Mori, Rebecca L Peterson, Timothy J Leedham, J Rickard, Henning SirringhausAbstract:A low-temperature, solution-based preparation of amorphous, metal oxide semiconducting thin-films is reported. This ‘sol–gel on Chip’ hydrolysis approach yields thin-film transistors with high field-effect mobilities, reproducible and stable turn-on voltages and high operational stability. At present there is no ‘ideal’ thin-film transistor technology for demanding display applications, such as organic light-emitting diode displays, that allows combining the low-temperature, solution-Processability offered by organic semiconductors with the high level of performance achievable with microcrystalline silicon^ 1 . N-type amorphous mixed metal oxide semiconductors, such as ternary oxides M_ x ^1M_ y ^2O_ z , where M^1 and M^2 are metals such as In, Ga, Sn, or Zn, have recently gained momentum because of their high carrier mobility and stability^ 2 , 3 and good optical transparency, but they are mostly deposited by sputtering. So far no route is available for forming high-performance mixed oxide materials from solution at low Process temperatures
Rebecca L Peterson - One of the best experts on this subject based on the ideXlab platform.
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low temperature high performance solution Processed metal oxide thin film transistors formed by a sol gel on Chip Process
Nature Materials, 2011Co-Authors: Kulbinder K Banger, Yoshihisa Yamashita, Kiyotaka Mori, Rebecca L Peterson, Timothy J Leedham, J Rickard, Henning SirringhausAbstract:A low-temperature, solution-based preparation of amorphous, metal oxide semiconducting thin-films is reported. This ‘sol–gel on Chip’ hydrolysis approach yields thin-film transistors with high field-effect mobilities, reproducible and stable turn-on voltages and high operational stability.
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Low-temperature, high-performance solution-Processed metal oxide thin-film transistors formed by a ‘sol–gel on Chip’ Process
Nature Materials, 2011Co-Authors: Kulbinder K Banger, Yoshihisa Yamashita, Kiyotaka Mori, Rebecca L Peterson, Timothy J Leedham, J Rickard, Henning SirringhausAbstract:A low-temperature, solution-based preparation of amorphous, metal oxide semiconducting thin-films is reported. This ‘sol–gel on Chip’ hydrolysis approach yields thin-film transistors with high field-effect mobilities, reproducible and stable turn-on voltages and high operational stability. At present there is no ‘ideal’ thin-film transistor technology for demanding display applications, such as organic light-emitting diode displays, that allows combining the low-temperature, solution-Processability offered by organic semiconductors with the high level of performance achievable with microcrystalline silicon^ 1 . N-type amorphous mixed metal oxide semiconductors, such as ternary oxides M_ x ^1M_ y ^2O_ z , where M^1 and M^2 are metals such as In, Ga, Sn, or Zn, have recently gained momentum because of their high carrier mobility and stability^ 2 , 3 and good optical transparency, but they are mostly deposited by sputtering. So far no route is available for forming high-performance mixed oxide materials from solution at low Process temperatures
Kulbinder K Banger - One of the best experts on this subject based on the ideXlab platform.
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low temperature high performance solution Processed metal oxide thin film transistors formed by a sol gel on Chip Process
Nature Materials, 2011Co-Authors: Kulbinder K Banger, Yoshihisa Yamashita, Kiyotaka Mori, Rebecca L Peterson, Timothy J Leedham, J Rickard, Henning SirringhausAbstract:A low-temperature, solution-based preparation of amorphous, metal oxide semiconducting thin-films is reported. This ‘sol–gel on Chip’ hydrolysis approach yields thin-film transistors with high field-effect mobilities, reproducible and stable turn-on voltages and high operational stability.
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Low-temperature, high-performance solution-Processed metal oxide thin-film transistors formed by a ‘sol–gel on Chip’ Process
Nature Materials, 2011Co-Authors: Kulbinder K Banger, Yoshihisa Yamashita, Kiyotaka Mori, Rebecca L Peterson, Timothy J Leedham, J Rickard, Henning SirringhausAbstract:A low-temperature, solution-based preparation of amorphous, metal oxide semiconducting thin-films is reported. This ‘sol–gel on Chip’ hydrolysis approach yields thin-film transistors with high field-effect mobilities, reproducible and stable turn-on voltages and high operational stability. At present there is no ‘ideal’ thin-film transistor technology for demanding display applications, such as organic light-emitting diode displays, that allows combining the low-temperature, solution-Processability offered by organic semiconductors with the high level of performance achievable with microcrystalline silicon^ 1 . N-type amorphous mixed metal oxide semiconductors, such as ternary oxides M_ x ^1M_ y ^2O_ z , where M^1 and M^2 are metals such as In, Ga, Sn, or Zn, have recently gained momentum because of their high carrier mobility and stability^ 2 , 3 and good optical transparency, but they are mostly deposited by sputtering. So far no route is available for forming high-performance mixed oxide materials from solution at low Process temperatures
W.m. Chen - One of the best experts on this subject based on the ideXlab platform.
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E valuation of mechanical stresses in silicon substrates due to lead-tin solder bumps via synchrotron X-ray topography and finite element modeling
2003Co-Authors: J. Kanatharana, T. Buckley, Patrick J. Mcnally, T. O. Tuomi, D. Lowney, W.m. Chen, R. Rantamäki, L. Knuuttila, Juha RiikonenAbstract:Solder-based flip-Chip packaging has prompted interest in integrated circuit (IC) packaging applications due to its many advantages in terms of cost, package size, electrical performance, input / output density, etc. The ball grid array (BGA) is one of the most common flip-Chip packaging techniques used for microProcessor applications. However, mechanical stresses induced by the flip-Chip Process can impact adversely on the reliability of products. Synchrotron X-ray topography (SXRT), a non-destructive technique, has been employed to investigate the spatial extent of strain fields imposed on the underlying silicon substrate for Intel Pentium III microProcessors due to the lead-tin solder bump Process for BGA packaging. Large area and section back-reflection SXRT images were taken before and after a simulation of the reflow Process at 350 8C in atmosphere. The presence of induced strain fields in the Si substrate due to the overlying bump structures has been observed via the extinction contrast effect in these X-ray topographs. In addition, orientational contrast effects have also been found after the reflow Process due to the severe stresses in the underlying silicon beneath the lead bumps. The estimated magnitudes of stress, usu, imposed on the underlying silicon were calculated to be of the order of 100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the lead bumps were removed from the wafer, which confirms that the bumps are indeed a major source of strain in the underlying Si. Finite element modeling (FEM) has also been performed in two-dimensional (2-D) plane strain mode. The magnitudes and spatial distribution of the stresses after the reflow Process are in good agreement with the SXRT results. 2003 Elsevier Science B.V. All rights reserved.
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Evaluation of mechanical stresses in silicon substrates due to lead-tin solder bumps via synchrotron X-ray topography and finite element modeling
Microelectronic Engineering, 2003Co-Authors: J. Kanatharana, J. J. Pérez-camacho, T. Buckley, Patrick J. Mcnally, T. O. Tuomi, A. N. Danilewsky, M. O'hare, D. Lowney, W.m. Chen, R. RantamäkiAbstract:Solder-based flip-Chip packaging has prompted interest in integrated circuit (IC) packaging applications due to its many advantages in terms of cost, package size, electrical performance, input/output density, etc. The ball grid array (BGA) is one of the most common flip-Chip packaging techniques used for microProcessor applications. However, mechanical stresses induced by the flip-Chip Process can impact adversely on the reliability of products. Synchrotron X-ray topography (SXRT), a non-destructive technique, has been employed to investigate the spatial extent of strain fields imposed on the underlying silicon substrate for Intel® Pentium® III microProcessors due to the lead-tin solder bump Process for BGA packaging. Large area and section back-reflection SXRT images were taken before and after a simulation of the reflow Process at 350 °C in atmosphere. The presence of induced strain fields in the Si substrate due to the overlying bump structures has been observed via the extinction contrast effect in these X-ray topographs. In addition, orientational contrast effects have also been found after the reflow Process due to the severe stresses in the underlying silicon beneath the lead bumps. The estimated magnitudes of stress, |σ|, imposed on the underlying silicon were calculated to be of the order of 100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the lead bumps were removed from the wafer, which confirms that the bumps are indeed a major source of strain in the underlying Si. Finite element modeling (FEM) has also been performed in two-dimensional (2-D) plane strain mode. The magnitudes and spatial distribution of the stresses after the reflow Process are in good agreement with the SXRT results.
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Examination of mechanical stresses in silicon substrates due to lead–tin solder bumps via micro-Raman spectroscopy and finite element modelling
Semiconductor Science and Technology, 2002Co-Authors: J. Kanatharana, J. J. Pérez-camacho, T. Buckley, Patrick J. Mcnally, T. O. Tuomi, Juha Riikonen, A. N. Danilewsky, M. O'hare, D. Lowney, W.m. ChenAbstract:Due to the fact that semiconductor devices have decreased significantly in geometry and increased enormously in electronic design complication, flip-Chip packaging technology was launched to increase input/output count, improve electrical performance, reduce packaging size and be cost effective. The Intel®Pentium®III microProcessor uses the popular ball grid array (BGA) packaging technique. BGA is one of the most common flip-Chip packaging techniques used for microProcessor applications. However, mechanical stresses induced by the flip-Chip Process are major concerns for the reliability of such devices. Micro-Raman spectroscopy (μRS) is a powerful technique for investigating the spatial extent of strain fields in microelectronic devices. In this study, the strain fields imposed on the underlying silicon substrate due to the lead–tin solder bump Process in BGA packaging have been investigated in pre- and post-reflowed samples using μRS and finite element modelling (FEM). For pre-reflowed samples, an approximate uniaxial compressive stress of 200 MPa is developed near the edge of the under bump metallization (UBM). However, a tensile stress up to ~300 MPa is found for post-reflowed samples. Two-dimensional (2D) plane strain FEM has also been performed. The magnitudes and spatial distribution of the stresses after the reflow Process are in good agreement with the micro-Raman results.
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Investigation of Mechanical Stresses in Underlying Silicon due to Lead-Tin Solder Bumps via Synchrotron X-Ray Topography and Finite Element Analysis
MRS Proceedings, 2001Co-Authors: J. Kanatharana, J. J. Pérez-camacho, T. Buckley, Patrick J. Mcnally, T. O. Tuomi, A. N. Danilewsky, M. O'hare, D. Lowney, W.m. ChenAbstract:ABSTRACTSolder based flip-Chip packaging has prompted interest in many integrated circuit (IC)packaging applications due to its many advantages in terms of cost, package size, electricalperformance, input/output density, etc. The ball grid array (BGA) is one of the most commonflip-Chip packaging techniques used for microProcessor applications. However, mechanicalstresses induced by the flip-Chip Process can impact adversely on the reliability of production.White beam synchrotron x-ray topography (SXRT), a non-destructive technique, has beenemployed to investigate the spatial extent of strain fields imposed on the underlying siliconsubstrate for Intelν®Pentiumν®III microProcessors due to the lead-tin solder bump Process for BGApackaging. Large area and section back-reflection SXRT images were taken before and after asimulation of the reflow Process at 350°C in atmosphere. The presence of induced strain fields inthe Si substrate due to the overlying bump structures has been observed via the extinction contrasteffect in these x-ray topographs. In addition, orientational contrast effects have also been foundafter the reflow Process due to the severe stresses in the underlying silicon beneath the lead bumps.The estimated magnitudes of stress, ∣σ∣, imposed on the underlying silicon were calculated to be100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the leadbumps were removed from the wafer, which confirms that the bumps are indeed a major source ofstrain in the underlying Si. Finite element analysis (FEA) has also been performed in 2-D planestrain mode. The magnitudes and spatial distribution of the stresses after the reflow Process are ingood agreement with the SXRT results.
Hidetoshi Onodera - One of the best experts on this subject based on the ideXlab platform.
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wide supply range all digital leakage variation sensor for on Chip Process and temperature monitoring
IEEE Journal of Solid-state Circuits, 2015Co-Authors: A Mahfuzul K M Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi OnoderaAbstract:Variation in Process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-Chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking Process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test Chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 µm 2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product Chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.
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wide supply range all digital leakage variation sensor for on Chip Process and temperature monitoring
Asian Solid-State Circuits Conference, 2014Co-Authors: A Mahfuzul K M Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi OnoderaAbstract:Variation in Process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-Chip circuit to monitor leakage current variations of both of the nMOSFET and pMOS-FET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking Process and temperature. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. An estimation method of threshold voltage variation is then developed. Cell-base design approach is taken so that design cost is minimized. Measurement results from a 65-nm test Chip show the validity of the proposed circuit. Total area is 4500 μm2 and active power consumption is 50 nW at 1.0 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product Chips for applications such as testing and post-silicon tuning.