The Experts below are selected from a list of 236085 Experts worldwide ranked by ideXlab platform

De Gyvez, José Pineda - One of the best experts on this subject based on the ideXlab platform.

  • Multi-bit pulsed-latch based low power synchronous Circuit Design
    IEEE Computer Society, 2018
    Co-Authors: Singh Kamlesh, Rosas, Omar Alejandro Rodriguez, Jiao Hailong, Huisken Jos, De Gyvez, José Pineda
    Abstract:

    Pulsed-latches emerge as an ideal sequencing element for low power digital Circuit Design, serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital Circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial Design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark Circuits and an ARM Cortex-M0 as compared to the flip-flop based Designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based Designs

Pineda De Gyvez, J José - One of the best experts on this subject based on the ideXlab platform.

  • Multi-bit pulsed-latch based low power synchronous Circuit Design
    IEEE Computer Society, 2018
    Co-Authors: Kk Singh, Oa ,rodriguez Rosas, Jiao H Hailong, Huisken, Ja Jos, Pineda De Gyvez, J José
    Abstract:

    \u3cp\u3ePulsed-latches emerge as an ideal sequencing element for low power digital Circuit Design, serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital Circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial Design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark Circuits and an ARM Cortex-M0 as compared to the flip-flop based Designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based Designs.\u3c/p\u3

Willy Sansen - One of the best experts on this subject based on the ideXlab platform.

  • analog Circuit Design in scaled cmos technology
    Symposium on VLSI Circuits, 1996
    Co-Authors: Willy Sansen
    Abstract:

    Scaled CMOS technology gives rise to submicron devices. In such devices short-channel effects lead to shifts in threshold voltage, increased mismatch and noise. The velocity saturation limits the obtainable transconductance and hence also the high speed performance. Lower supply voltages require the operational amplifier building block to operate rail-to-rail. In delta-sigma converters this leads to very-low-power converters. Considerable attention goes to Circuit Design for telecommunication applications, in which the inductor is making a comeback. The ultimate challenge of analog Design however is the cointegration with digital blocks, causing coupling noise and requiring sophisticated tools.

Jacob R Baker - One of the best experts on this subject based on the ideXlab platform.

  • dram Circuit Design fundamental and high speed topics
    2007
    Co-Authors: Brent Keeth, Jacob R Baker, Brian Johnson
    Abstract:

    A modern, comprehensive introduction to DRAM for students and practicing chip Designers Dynamic Random Access Memory (DRAM) technology has been one of the greatestdriving forces in the advancement of solid-state technology. With its ability to produce high product volumes and low pricing, it forces solid-state memory manufacturers to work aggressively to cut costs while maintaining, if not increasing, their market share. As a result, the state of the art continues to advance owing to the tremendous pressure to get more memory chips from each silicon wafer, primarily through process scaling and clever Design. From a team of engineers working in memory Circuit Design, DRAM Circuit Design gives students and practicing chip Designers an easy-to-follow, yet thorough, introductory treatment of the subject. Focusing on the chip Designer rather than the end user, this volume offers expanded, up-to-date coverage of DRAM Circuit Design by presenting both standard and high-speed implementations. Additionally, it explores a range of topics: the DRAM array, peripheral Circuitry, global Circuitry and considerations, voltage converters, synchronization in DRAMs, data path Design, and power delivery. Additionally, this up-to-date and comprehensive book features topics in high-speed Design and architecture and the ever-increasing speed requirements of memory Circuits. The only book that covers the breadth and scope of the subject under one cover, DRAM Circuit Design is an invaluable introduction for students in courses on memory Circuit Design or advanced digital courses in VLSI or CMOS Circuit Design. It also serves as an essential, one-stop resource for academics, researchers, and practicing engineers.

  • cmos Circuit Design layout and simulation
    1997
    Co-Authors: Jacob R Baker
    Abstract:

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical Design of both analog and digital integrated Circuits, offering a vital, contemporary view of a wide range of analog/digital Circuit blocks including: phase-locked-loops, delta-sigma sensing Circuits, voltage/current references, op-amps, the Design of data converters, and much more. Regardless of one's integrated Circuit (IC) Design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC Design via detailed derivations, discussions, and hundreds of Design, layout, and simulation examples.

  • cmos Circuit Design layout and simulation
    1997
    Co-Authors: Jacob R Baker
    Abstract:

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical Design of both analog and digital integrated Circuits, offering a vital, contemporary view of a wide range of analog/digital Circuit blocks including: phase-locked-loops, delta-sigma sensing Circuits, voltage/current references, op-amps, the Design of data converters, and much more. Regardless of one's integrated Circuit (IC) Design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC Design via detailed derivations, discussions, and hundreds of Design, layout, and simulation examples.

Singh Kamlesh - One of the best experts on this subject based on the ideXlab platform.

  • Multi-bit pulsed-latch based low power synchronous Circuit Design
    IEEE Computer Society, 2018
    Co-Authors: Singh Kamlesh, Rosas, Omar Alejandro Rodriguez, Jiao Hailong, Huisken Jos, De Gyvez, José Pineda
    Abstract:

    Pulsed-latches emerge as an ideal sequencing element for low power digital Circuit Design, serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital Circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial Design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark Circuits and an ARM Cortex-M0 as compared to the flip-flop based Designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based Designs