The Experts below are selected from a list of 150 Experts worldwide ranked by ideXlab platform
Minkyu Song - One of the best experts on this subject based on the ideXlab platform.
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A Clock Feedthrough reduction circuit for switched-current systems
IEEE Journal of Solid-State Circuits, 1993Co-Authors: Minkyu SongAbstract:A Clock Feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent Clock Feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 mu m CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of Clock Feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20%.
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A new Clock Feedthrough reduction circuit in switched-current filters
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems, 1992Co-Authors: Minkyu SongAbstract:A novel Clock Feedthrough reduction circuit which is helpful in the design of switched-current filters is proposed. This circuit uses the cancellation technique. A switched-current FIR (finite impulse response) filter adopting the proposed circuit is designed. Simulation of the prototype filter circuit reveals good results. It has a small chip area and higher operating frequency in comparison with the conventional methods.
J.l. Huertas - One of the best experts on this subject based on the ideXlab platform.
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A study of the sensitivity of switched-current wave analog filters to mismatching and Clock-Feedthrough errors
1994 IEEE International Symposium on Circuits and Systems (ISCAS), 1994Co-Authors: A. Yufera, A. Rueda, J.l. HuertasAbstract:The influence of the main source of errors in Switched-Current (SI) filters over the performance of Wave Analog Filters (WAE) is evaluated. Models of mismatching and Clock-Feedthrough (CF) are deduced for basic building blocks, and applied to study the sensitivity of a third-order filter. Monte Carlo simulations performed using a behavior simulator prove that CF are dominant over mismatching effects.
A. Yufera - One of the best experts on this subject based on the ideXlab platform.
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Studying the effects of mismatching and Clock-Feedthrough in switched-current filters using behavioral simulation
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1997Co-Authors: A. Yufera, A. RuedaAbstract:Mismatching and Clock-Feedthrough are sources of error in Switched-Current (SI) circuits producing DC offset, gain errors, and harmonic distortion, which cause deviations in SI filter responses in both the passband and the stopband. This paper develops formulas including these effects in the input-output description of filter building blocks to make possible not only a faster prediction of the filter performance levels but also to analyze tradeoffs at the early design stages. The block input-output descriptions have been derived taking into account the real physical realization of these blocks together with simple error models. Using these behavioral input-output descriptions, we have studied the extent of these effects in the performance of two different SI filter realizations of passive LC ladder structures: one using integrators to simulate the signal flow graph (SFG) of the ladder and another based on the use of wave active filter (WAF) structures. Monte Carlo simulations of a filter example are presented and analyzed.
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A study of the sensitivity of switched-current wave analog filters to mismatching and Clock-Feedthrough errors
1994 IEEE International Symposium on Circuits and Systems (ISCAS), 1994Co-Authors: A. Yufera, A. Rueda, J.l. HuertasAbstract:The influence of the main source of errors in Switched-Current (SI) filters over the performance of Wave Analog Filters (WAE) is evaluated. Models of mismatching and Clock-Feedthrough (CF) are deduced for basic building blocks, and applied to study the sensitivity of a third-order filter. Monte Carlo simulations performed using a behavior simulator prove that CF are dominant over mismatching effects.
Chih-wei Hu - One of the best experts on this subject based on the ideXlab platform.
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The design of a delta-sigma modulator with low Clock Feedthrough noise, op-amp gain compensation, and more correctly transferring charges between capacitors
1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997Co-Authors: Jen-shiun Chiang, Chih-wei HuAbstract:The performance of a delta-sigma modulator (/spl Delta/ /spl Sigma/M) is degraded due to the low op-amp gain, the Clock Feedthrough noise, and the right or fault of charge transferring between capacitors. Hurst et al. in 1993 suggested an architecture which uses reduced sensitivity to the op-amp gain. Since the low op-amp gain is much easier to design and makes the design of a /spl Delta/ /spl Sigma/M become very easy. However, they do not overcome the noise effect of the /spl Delta/ /spl Sigma/M. Here, another design is proposed and the effect of noise is reduced.
E.g. Friedman - One of the best experts on this subject based on the ideXlab platform.
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Clock Feedthrough in cmos analog transmission gate switches
Analog Integrated Circuits and Signal Processing, 2005Co-Authors: Weize Xu, E.g. FriedmanAbstract:An analysis of Clock Feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for Clock Feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the Clock Feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing Clock Feedthrough noise. A model of Clock Feedthrough noise as compared with SPICE simulations exhibits less than 3% error.
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Clock Feedthrough in CMOS analog transmission gate switches
15th Annual IEEE International ASIC SOC Conference, 2002Co-Authors: Weize Xu, E.g. FriedmanAbstract:An analysis of Clock Feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for Clock Feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. Coupling from overlap and MOSFET gate capacitors causes Clock Feedthrough in TG switches. The slower gate voltage transition provides additional time for the MOSFET to compensate the coupling error on the sample and hold (S/H) capacitor, yielding a smaller Clock Feedthrough error.
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A CMOS Miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and Clock Feedthrough
15th Annual IEEE International ASIC SOC Conference, 2002Co-Authors: Weize Xu, E.g. FriedmanAbstract:A technique using Miller capacitance in the sample-and-hold (S/H) circuit is introduced in this paper to reduce the charge sharing effect (CSE) due to the parasitic capacitance and Clock Feedthrough from a sampling switch. A compact cascode amplifier is used in the Miller feedback circuit and a ten times reduction in CSE and Clock Feedthrough is achieved. The S/H capacitor is split into two parts, C/sub sh1/ and C/sub sh2/. One of these S/H capacitors effectively reduces the CSE while the other capacitor reduces Clock Feedthrough.