The Experts below are selected from a list of 1323 Experts worldwide ranked by ideXlab platform
Andreas Demosthenous - One of the best experts on this subject based on the ideXlab platform.
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constant resistance cmos input Sampling Switch for gsm wcdma high dynamic range delta sigma modulators
IEEE Transactions on Circuits and Systems I-regular Papers, 2008Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The nonlinearity of the input Sampling Switch in a Switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper. A linearized CMOS Switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling circuit, compared to using a standard CMOS Switch or a bootstrapped nMOS Switch. The dynamic range improvement achieved as a result of the proposed technique is validated with the design of two high dynamic range fourth-order Switched-capacitor DeltaSigma modulators for GSM and WCDMA radio standards in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm2 .
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Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range Delta Sigma Modulators
IEEE T CIRCUITS-I, 2008Co-Authors: Andreas DemosthenousAbstract:The nonlinearity of the input Sampling Switch in a Switched-capacitor delta-sigma (Delta Sigma) analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper. A linearized CMOS Switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling circuit, compared to using a standard CMOS Switch or a bootstrapped nMOS Switch. The dynamic range improvement achieved as a result of the proposed technique is validated with the design of two high dynamic range fourth-order Switched-capacitor Delta Sigma modulators for GSM and WCDMA radio standards in a 0.35-mu m BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm(2).
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Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range Modulators
2008Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The nonlinearity of the input Sampling Switch in a Switched-capacitor delta-sigma analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper. A linearized CMOS Switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling circuit, compared to using a standard CMOS Switch or a bootstrapped nMOS Switch. The dynamic range improvement achieved as a result of the pro- posed technique is validated with the design of two high dynamic range fourth-order Switched-capacitor modulators for GSM and WCDMA radio standards in a 0.35- m BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm . Index Terms—Analog-to-digital conversion (ADC), bootstrap circuit, CMOS Switch linearization, delta-sigma modulation, GSM, nonlinearity, radio receivers, Switched-capacitor circuits, WCDMA.
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constant resistance cmos input Sampling Switch for gsm wcdma high dynamic range modulators
2008Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The nonlinearity of the input Sampling Switch in a Switched-capacitor delta-sigma analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper. A linearized CMOS Switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling circuit, compared to using a standard CMOS Switch or a bootstrapped nMOS Switch. The dynamic range improvement achieved as a result of the pro- posed technique is validated with the design of two high dynamic range fourth-order Switched-capacitor modulators for GSM and WCDMA radio standards in a 0.35- m BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm . Index Terms—Analog-to-digital conversion (ADC), bootstrap circuit, CMOS Switch linearization, delta-sigma modulation, GSM, nonlinearity, radio receivers, Switched-capacitor circuits, WCDMA.
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A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB SFDR using constant resistance CMOS input Sampling Switch
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The performance of a Switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is greatly degraded by the linearity of the input Sampling Switch. This is especially so in older cheaper technologies where very-low threshold voltage devices are unavailable. To address the input Switch Sampling distortion issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper, featuring a constant on- resistance over the entire input signal range. The dynamic range improvement with the proposed approach is validated with the design of a fourth-order, Switched-capacitor DeltaSigma modulator for WCDMA in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 77 dB is achieved at a clock-rate of 153.6 MHz. The modulator dissipates 14 mW from a 2.7-V power supply and occupies an area of 0.2 mm2.
Olujide A. Adeniran - One of the best experts on this subject based on the ideXlab platform.
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constant resistance cmos input Sampling Switch for gsm wcdma high dynamic range delta sigma modulators
IEEE Transactions on Circuits and Systems I-regular Papers, 2008Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The nonlinearity of the input Sampling Switch in a Switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper. A linearized CMOS Switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling circuit, compared to using a standard CMOS Switch or a bootstrapped nMOS Switch. The dynamic range improvement achieved as a result of the proposed technique is validated with the design of two high dynamic range fourth-order Switched-capacitor DeltaSigma modulators for GSM and WCDMA radio standards in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm2 .
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Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range Modulators
2008Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The nonlinearity of the input Sampling Switch in a Switched-capacitor delta-sigma analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper. A linearized CMOS Switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling circuit, compared to using a standard CMOS Switch or a bootstrapped nMOS Switch. The dynamic range improvement achieved as a result of the pro- posed technique is validated with the design of two high dynamic range fourth-order Switched-capacitor modulators for GSM and WCDMA radio standards in a 0.35- m BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm . Index Terms—Analog-to-digital conversion (ADC), bootstrap circuit, CMOS Switch linearization, delta-sigma modulation, GSM, nonlinearity, radio receivers, Switched-capacitor circuits, WCDMA.
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constant resistance cmos input Sampling Switch for gsm wcdma high dynamic range modulators
2008Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The nonlinearity of the input Sampling Switch in a Switched-capacitor delta-sigma analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper. A linearized CMOS Switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling circuit, compared to using a standard CMOS Switch or a bootstrapped nMOS Switch. The dynamic range improvement achieved as a result of the pro- posed technique is validated with the design of two high dynamic range fourth-order Switched-capacitor modulators for GSM and WCDMA radio standards in a 0.35- m BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm . Index Terms—Analog-to-digital conversion (ADC), bootstrap circuit, CMOS Switch linearization, delta-sigma modulation, GSM, nonlinearity, radio receivers, Switched-capacitor circuits, WCDMA.
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A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB SFDR using constant resistance CMOS input Sampling Switch
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007Co-Authors: Olujide A. Adeniran, Andreas DemosthenousAbstract:The performance of a Switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is greatly degraded by the linearity of the input Sampling Switch. This is especially so in older cheaper technologies where very-low threshold voltage devices are unavailable. To address the input Switch Sampling distortion issue, the use of an optimized bootstrapped CMOS Switch is proposed in this paper, featuring a constant on- resistance over the entire input signal range. The dynamic range improvement with the proposed approach is validated with the design of a fourth-order, Switched-capacitor DeltaSigma modulator for WCDMA in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 77 dB is achieved at a clock-rate of 153.6 MHz. The modulator dissipates 14 mW from a 2.7-V power supply and occupies an area of 0.2 mm2.
Omid Hashemipour - One of the best experts on this subject based on the ideXlab platform.
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a reliable full swing low distortion cmos bootstrapped Sampling Switch
International Conference on Electronics Circuits and Systems, 2011Co-Authors: Mohammad Reza Asgari, Seyyed Hossein Pishgar, Omid HashemipourAbstract:A reliable low-distortion CMOS bootstrapped Sampling Switch is presented. Compared to conventional bootstrapped Switch, this scheme achieves more reliability because the limits of proposed circuit are V DD +V THn and −|V THp |. The variation of equivalent conductance of this CMOS Sampling Switch through input signal is alleviated by a specific Switch's voltage control. The proposed Switch is realized with the half number of transistors compared to previously reported scheme which results more simplicity and less area. Simulations using a standard 0.18μm CMOS technology model show about 10dB improvements in both THD and SFDR while using it in a conventional fully-differential sample-and-hold circuit.
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ICECS - A reliable full-swing low-distortion CMOS bootstrapped Sampling Switch
2011 18th IEEE International Conference on Electronics Circuits and Systems, 2011Co-Authors: Mohammad Reza Asgari, Seyyed Hossein Pishgar, Omid HashemipourAbstract:A reliable low-distortion CMOS bootstrapped Sampling Switch is presented. Compared to conventional bootstrapped Switch, this scheme achieves more reliability because the limits of proposed circuit are V DD +V THn and −|V THp |. The variation of equivalent conductance of this CMOS Sampling Switch through input signal is alleviated by a specific Switch's voltage control. The proposed Switch is realized with the half number of transistors compared to previously reported scheme which results more simplicity and less area. Simulations using a standard 0.18μm CMOS technology model show about 10dB improvements in both THD and SFDR while using it in a conventional fully-differential sample-and-hold circuit.
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Body effect compensation of analog Switches using variable voltage function
IEICE Electronics Express, 2011Co-Authors: Mohammad Reza Asgari, Omid HashemipourAbstract:This paper introduces a new technique for reducing the body effect on the channel on-resistance of analog Switches. In this technique, the gate of bootstrapped Sampling Switch tracks the input signal with a variable voltage function. Rail-to-rail performance of proposed Switch makes it suitable for low voltage applications. The simulation results show that the proposed technique can significantly improve the dynamic performance of a sample-and-hold circuit.
Chungchih Hung - One of the best experts on this subject based on the ideXlab platform.
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A Reliable Low-Voltage Low-Distortion MOS Analog Switch
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2006Co-Authors: Chunyueh Yang, Chungchih HungAbstract:A novel low-voltage low-distortion analog Sampling Switch is proposed in this letter. A "source tracker" techniuqe is used to distinguish the real source terminal of the Sampling Switch. The turn-on resistance of the Sampling Switch is kept exactly constant. The modified Switch makes the rail-to-rail input signal swing possible for low voltage. TSMC 0.18 μm standard CMOS technology is utilized in this research. Results indicate that much lower Total Harmonic Distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of the low-voltage low-distortion Switched-capacitor circuits.
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a low voltage low distortion mos Sampling Switch
International Symposium on Circuits and Systems, 2005Co-Authors: Chunyueh Yang, Chungchih HungAbstract:In order to reduce distortion due to variation of the gate overdrive and the threshold voltage, a novel low-voltage constant-resistance Sampling Switch is proposed. The technique to reduce nonlinearity can be used in a high resolution sample-and-hold circuit. TSMC 0.18 /spl mu/m standard CMOS technology is used. Results indicate that much lower total harmonic distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of low-voltage low-distortion Switched-capacitor circuits.
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ISCAS (4) - A low-voltage low-distortion MOS Sampling Switch
2005 IEEE International Symposium on Circuits and Systems, 1Co-Authors: Chunyueh Yang, Chungchih HungAbstract:In order to reduce distortion due to variation of the gate overdrive and the threshold voltage, a novel low-voltage constant-resistance Sampling Switch is proposed. The technique to reduce nonlinearity can be used in a high resolution sample-and-hold circuit. TSMC 0.18 /spl mu/m standard CMOS technology is used. Results indicate that much lower total harmonic distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of low-voltage low-distortion Switched-capacitor circuits.
Mohammad Reza Asgari - One of the best experts on this subject based on the ideXlab platform.
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a reliable full swing low distortion cmos bootstrapped Sampling Switch
International Conference on Electronics Circuits and Systems, 2011Co-Authors: Mohammad Reza Asgari, Seyyed Hossein Pishgar, Omid HashemipourAbstract:A reliable low-distortion CMOS bootstrapped Sampling Switch is presented. Compared to conventional bootstrapped Switch, this scheme achieves more reliability because the limits of proposed circuit are V DD +V THn and −|V THp |. The variation of equivalent conductance of this CMOS Sampling Switch through input signal is alleviated by a specific Switch's voltage control. The proposed Switch is realized with the half number of transistors compared to previously reported scheme which results more simplicity and less area. Simulations using a standard 0.18μm CMOS technology model show about 10dB improvements in both THD and SFDR while using it in a conventional fully-differential sample-and-hold circuit.
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ICECS - A reliable full-swing low-distortion CMOS bootstrapped Sampling Switch
2011 18th IEEE International Conference on Electronics Circuits and Systems, 2011Co-Authors: Mohammad Reza Asgari, Seyyed Hossein Pishgar, Omid HashemipourAbstract:A reliable low-distortion CMOS bootstrapped Sampling Switch is presented. Compared to conventional bootstrapped Switch, this scheme achieves more reliability because the limits of proposed circuit are V DD +V THn and −|V THp |. The variation of equivalent conductance of this CMOS Sampling Switch through input signal is alleviated by a specific Switch's voltage control. The proposed Switch is realized with the half number of transistors compared to previously reported scheme which results more simplicity and less area. Simulations using a standard 0.18μm CMOS technology model show about 10dB improvements in both THD and SFDR while using it in a conventional fully-differential sample-and-hold circuit.
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Body effect compensation of analog Switches using variable voltage function
IEICE Electronics Express, 2011Co-Authors: Mohammad Reza Asgari, Omid HashemipourAbstract:This paper introduces a new technique for reducing the body effect on the channel on-resistance of analog Switches. In this technique, the gate of bootstrapped Sampling Switch tracks the input signal with a variable voltage function. Rail-to-rail performance of proposed Switch makes it suitable for low voltage applications. The simulation results show that the proposed technique can significantly improve the dynamic performance of a sample-and-hold circuit.
