The Experts below are selected from a list of 312 Experts worldwide ranked by ideXlab platform
Bart Nauwelaers - One of the best experts on this subject based on the ideXlab platform.
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Design and characterization of CPW Feedthroughs in multilayer thin film MCM-D
The International journal of microcircuits and electronic packaging, 2020Co-Authors: G. Carchon, W. De Raedt, Bart Nauwelaers, E. BeyneAbstract:In this publication, the researchers report on the design and characterization of CPW Feedthroughs for RF and microwave applications in multilayer thin film MCM-D. The Feedthrough is based on an inverted multilayer microstrip line and two CPW-to-microstrip transitions. The bottom of the vertical metal wall is used as the ground-plane of the intrinsic Feedthrough. Using 3-D simulations, it is shown that, for design and analysis purposes, the vertical metal wall can be replaced by a thin metal layer with only a very small impact on the performance. This equivalent structure can be more easily fabricated and measured. This allows for a faster design and characterization of the Feedthrough. The transmission line properties (characteristic impedance and propagation constant) of the intrinsic Feedthrough are extracted based on the measurement of two equivalent structures with different length. Two types of Feedthroughs have been designed and realized. One design uses all-pass 50 Ω lines and can be used up to at least 50 GHz. The other design is realized on a different metal-layer and is based on a low-pass structure. It has a superior performance (insertion loss) up to 25 GHz. Measurements indicate that a low-loss (
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Design and characterization of CPW Feedthroughs in multi-layer thin-film MCM-D
2000 Asia-Pacific Microwave Conference. Proceedings (Cat. No.00TH8522), 2000Co-Authors: G. Carchon, W. De Raedt, Kristof Vaesen, Steven Brebels, Bart NauwelaersAbstract:We report on the design and characterization of CPW Feedthroughs for RF and microwave applications in multi-layer thin-film MCM-D. Using 3-D simulations, it is shown that, for analysis purposes, the vertical metal wall, can be replaced with a thin (5 /spl mu/m) metal layer with only a small impact on the actual performance. This equivalent structure can be more easily fabricated as the thin metal layer on the top is directly available in the multi-layer technology. This allows for a faster design and characterization of the Feedthrough. The transmission line properties (characteristic impedance and propagation constant) of the intrinsic Feedthrough are extracted based on the measurement of two equivalent lines with different length. Measurements indicate that a low-loss (
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Design and characterization of CPW Feedthroughs in multi-layer thin-film MCM-D
RAWCON 2000. 2000 IEEE Radio and Wireless Conference (Cat. No.00EX404), 2000Co-Authors: G. Carchon, W. De Raedt, Kristof Vaesen, Steven Brebels, O. Di Monaco, Bart NauwelaersAbstract:We report on the design and characterization of CPW Feedthroughs in multi-layer thin-film MCM-D. Using 3-D simulations, it is shown that, for analysis purposes, the vertical metal wall, can be replaced with a thin (5 /spl mu/m) metal layer with only a small impact on the actual performance. This equivalent structure can be more easily fabricated as the thin metal layer on the top is directly available in the multi-layer technology. This allows for a faster design and characterization of the Feedthrough. The transmission line properties (characteristic impedance and propagation constant) of the intrinsic Feedthrough are extracted based on the measurement of two equivalent lines with different length. Measurements indicate that a low-loss (
E.g. Friedman - One of the best experts on this subject based on the ideXlab platform.
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clock Feedthrough in cmos analog transmission gate switches
Analog Integrated Circuits and Signal Processing, 2005Co-Authors: Weize Xu, E.g. FriedmanAbstract:An analysis of clock Feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock Feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the clock Feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing clock Feedthrough noise. A model of clock Feedthrough noise as compared with SPICE simulations exhibits less than 3% error.
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Clock Feedthrough in CMOS analog transmission gate switches
15th Annual IEEE International ASIC SOC Conference, 2002Co-Authors: Weize Xu, E.g. FriedmanAbstract:An analysis of clock Feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock Feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. Coupling from overlap and MOSFET gate capacitors causes clock Feedthrough in TG switches. The slower gate voltage transition provides additional time for the MOSFET to compensate the coupling error on the sample and hold (S/H) capacitor, yielding a smaller clock Feedthrough error.
Weize Xu - One of the best experts on this subject based on the ideXlab platform.
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clock Feedthrough in cmos analog transmission gate switches
Analog Integrated Circuits and Signal Processing, 2005Co-Authors: Weize Xu, E.g. FriedmanAbstract:An analysis of clock Feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock Feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the clock Feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing clock Feedthrough noise. A model of clock Feedthrough noise as compared with SPICE simulations exhibits less than 3% error.
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Clock Feedthrough in CMOS analog transmission gate switches
15th Annual IEEE International ASIC SOC Conference, 2002Co-Authors: Weize Xu, E.g. FriedmanAbstract:An analysis of clock Feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock Feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. Coupling from overlap and MOSFET gate capacitors causes clock Feedthrough in TG switches. The slower gate voltage transition provides additional time for the MOSFET to compensate the coupling error on the sample and hold (S/H) capacitor, yielding a smaller clock Feedthrough error.
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A CMOS Miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock Feedthrough
15th Annual IEEE International ASIC SOC Conference, 2002Co-Authors: Weize Xu, E.g. FriedmanAbstract:A technique using Miller capacitance in the sample-and-hold (S/H) circuit is introduced in this paper to reduce the charge sharing effect (CSE) due to the parasitic capacitance and clock Feedthrough from a sampling switch. A compact cascode amplifier is used in the Miller feedback circuit and a ten times reduction in CSE and clock Feedthrough is achieved. The S/H capacitor is split into two parts, C/sub sh1/ and C/sub sh2/. One of these S/H capacitors effectively reduces the CSE while the other capacitor reduces clock Feedthrough.
Kamala Kanta Mahapatra - One of the best experts on this subject based on the ideXlab platform.
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Noise Tolerant Circuits for Modified Feedthrough Logic
2020Co-Authors: Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra, Kailash Chandra RoutAbstract:In this paper a circuit design technique to improve noise tolerant of a new CMOS domino logic family called Feedthrough logic is presented. The Feedthrough logic improves the performance of arithmetic circuit as compared to static CMOS and domino logic but its noise tolerant is very less. A 2-input NAND gate is designed by the proposed technique. The ANTE (average noise threshold energy) metric is used for the comparison of noise tolerance of proposed circuit with the Feedthrough logic. Simulation results for a 2- input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction leakage power.
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Performance analysis of modified Feedthrough logic for low power and high speed
IEEE-International Conference On Advances In Engineering Science And Management (ICAESM -2012), 2012Co-Authors: Sauvagya Ranjan Sahoo, Kamala Kanta MahapatraAbstract:In this paper the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called Feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrogh logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing Feedthrough logic and to further improve its speed we proposed another circuit which improves the speed by sacrificing dynamic power consumption. The proposed circuit is simulated using 0.18 μm, 1.8 V CMOS process technology. Intensive simulation results in Cadence environment shows that the proposed modified low-power structure reduces the dynamic power approximately by 35% and the modified structure for high performance achieves a speed up- 1.3 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing Feedthrough logic. The concept is validated through extensive simulation. The problem of requirement of output inverter and non-inverting logic are also completely eliminated in the proposed design.
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Modified circuit design technique for Feedthrough logic
2012 NATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION SYSTEMS, 2012Co-Authors: Sauvagya Ranjan Sahoo, Kamala Kanta MahapatraAbstract:In this paper a circuit design technique to reduce dynamic power consumption of a new CMOS domino logic family called feedthrogh logic is presented. The need for low power circuit with high speed has made it common practice to use Feedthrough logic. The proposed modified circuit has very low dynamic power consumption compared to recently proposed circuit techniques for Feedthrough logic styles. The proposed circuit is simulated using 0.18 μm, 1.8 V CMOS process technology. Intensive simulation results in cadence environment shows that the proposed modified circuit reduces the dynamic power consumption approximately 24% along with a significant reduction in power delay product, as compared to existing Feedthrough logic.
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Design of low power and high speed ripple carry adder using modified Feedthrough logic
2012 International Conference on Communications Devices and Intelligent Systems (CODIS), 2012Co-Authors: Sauvagya Ranjan Sahoo, Kamala Kanta MahapatraAbstract:This paper presents the design of a low power and high performance circuit using a new CMOS domino logic family called Feedthrough logic (FTL). Feedthrogh logic improves the performance of arithmetic circuit by performing partial evaluation in its computational block before its input signals are valid. FTL improves the speed of arithmetic circuits along with more power consumption. The proposed modified FTL achieves both reductions in average power consumption along with the improvement in speed at the cost of area. A long chain of inverter (10-stage) and a 16-bit ripple carry adder is designed by the proposed modified Feedthrough logic. Then a comparison analysis has been carried out by simulating the logic circuits in 0.18 um technology. The simulation shows that the proposed modified circuit reduces the dynamic power consumption up to 45% along with a improvement in speed by a factor of 1.65.
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A Low Power Circuit Technique for Feedthrough Logic
2011Co-Authors: Sauvagya Ranjan Sahoo, Kamala Kanta MahapatraAbstract:This paper presents the design of a low power dynamic circuit using a new CMOS domino logic family called Feedthrough logic. The proposed circuit has very low dynamic power consumption compared to the recently proposed circuit techniques for the dynamic logic styles. The proposed circuit has been simulated at 0.18 μm, 1.8 V CMOS process technology. Intensive simulation results in Cadence environment shows that the dynamic power reduces approximately by 40% for 10-stage of inverters and 4-bit ripple carry adder in comparison to existing Feedthrough logic. The problem of requirement of output inverter and noninverting logic are also completely eliminated in the proposed design. Keywords—CMOS logic circuits, Feedthrough logic (FTL), lowpower, adder.
G. Carchon - One of the best experts on this subject based on the ideXlab platform.
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Design and characterization of CPW Feedthroughs in multilayer thin film MCM-D
The International journal of microcircuits and electronic packaging, 2020Co-Authors: G. Carchon, W. De Raedt, Bart Nauwelaers, E. BeyneAbstract:In this publication, the researchers report on the design and characterization of CPW Feedthroughs for RF and microwave applications in multilayer thin film MCM-D. The Feedthrough is based on an inverted multilayer microstrip line and two CPW-to-microstrip transitions. The bottom of the vertical metal wall is used as the ground-plane of the intrinsic Feedthrough. Using 3-D simulations, it is shown that, for design and analysis purposes, the vertical metal wall can be replaced by a thin metal layer with only a very small impact on the performance. This equivalent structure can be more easily fabricated and measured. This allows for a faster design and characterization of the Feedthrough. The transmission line properties (characteristic impedance and propagation constant) of the intrinsic Feedthrough are extracted based on the measurement of two equivalent structures with different length. Two types of Feedthroughs have been designed and realized. One design uses all-pass 50 Ω lines and can be used up to at least 50 GHz. The other design is realized on a different metal-layer and is based on a low-pass structure. It has a superior performance (insertion loss) up to 25 GHz. Measurements indicate that a low-loss (
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Design and characterization of CPW Feedthroughs in multi-layer thin-film MCM-D
2000 Asia-Pacific Microwave Conference. Proceedings (Cat. No.00TH8522), 2000Co-Authors: G. Carchon, W. De Raedt, Kristof Vaesen, Steven Brebels, Bart NauwelaersAbstract:We report on the design and characterization of CPW Feedthroughs for RF and microwave applications in multi-layer thin-film MCM-D. Using 3-D simulations, it is shown that, for analysis purposes, the vertical metal wall, can be replaced with a thin (5 /spl mu/m) metal layer with only a small impact on the actual performance. This equivalent structure can be more easily fabricated as the thin metal layer on the top is directly available in the multi-layer technology. This allows for a faster design and characterization of the Feedthrough. The transmission line properties (characteristic impedance and propagation constant) of the intrinsic Feedthrough are extracted based on the measurement of two equivalent lines with different length. Measurements indicate that a low-loss (
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Design and characterization of CPW Feedthroughs in multi-layer thin-film MCM-D
RAWCON 2000. 2000 IEEE Radio and Wireless Conference (Cat. No.00EX404), 2000Co-Authors: G. Carchon, W. De Raedt, Kristof Vaesen, Steven Brebels, O. Di Monaco, Bart NauwelaersAbstract:We report on the design and characterization of CPW Feedthroughs in multi-layer thin-film MCM-D. Using 3-D simulations, it is shown that, for analysis purposes, the vertical metal wall, can be replaced with a thin (5 /spl mu/m) metal layer with only a small impact on the actual performance. This equivalent structure can be more easily fabricated as the thin metal layer on the top is directly available in the multi-layer technology. This allows for a faster design and characterization of the Feedthrough. The transmission line properties (characteristic impedance and propagation constant) of the intrinsic Feedthrough are extracted based on the measurement of two equivalent lines with different length. Measurements indicate that a low-loss (
