The Experts below are selected from a list of 5847 Experts worldwide ranked by ideXlab platform

Eby G. Friedman - One of the best experts on this subject based on the ideXlab platform.

  • timing optimization through Clock Skew scheduling
    2008
    Co-Authors: I.s. Kourtev, Baris Taskin, Eby G. Friedman
    Abstract:

    This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of Clock Skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.

  • DAC - Maximizing performance by retiming and Clock Skew scheduling
    Proceedings of the 36th ACM IEEE conference on Design automation conference - DAC '99, 1999
    Co-Authors: Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Abstract:

    The application of retiming and Clock Skew scheduling for improving the operating speed of synchronous circuits under setup and hold constraints is investigated in this paper. It is shown that when both long and short paths are considered, circuits optimized by the simultaneous application of retiming and Clock scheduling can achieve shorter Clock periods than optimized circuits generated by applying either of the two techniques separately. A mixed-integer linear programming formulation and an efficient heuristic are given for the problem of simultaneous retiming and Clock Skew scheduling under setup and hold constraints. Experiments with benchmark circuits demonstrate the efficiency of this heuristic and the effectiveness of the combined optimization. All of the test circuits show improvement. For more than half of them, the maximum operating speed increases by more than 21% over the optimized circuits obtained by applying retiming or Clock Skew scheduling separately.

  • Synthesis of Clock tree topologies to implement nonzero Clock Skew schedule
    IEE Proceedings - Circuits Devices and Systems, 1999
    Co-Authors: I.s. Kourtev, Eby G. Friedman
    Abstract:

    Designing the topology of a Clock distribution network is considered for a synchronous digital integrated circuit so as to satisfy a nonzero Clock Skew schedule. A methodology and related algorithms for synthesising the topology of the Clock distribution network from a Clock schedule derived from circuit timing information are presented. A new formulation of the problem of designing the Clock distribution network is given as an efficiently solvable integer linear programming problem. The approach is demonstrated on the suite of ISCAS'89 benchmark circuits. Up to 64% performance improvement is attained on these circuits by exploiting nonzero Clock Skew throughout the synchronous system. Clock tree topologies that implement the nonzero Clock Skew schedule based on the synthesis algorithms presented are described for each of the benchmark circuits.

  • Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations
    Journal of VLSI signal processing systems for signal image and video technology, 1997
    Co-Authors: Josè Luis Neves, Eby G. Friedman
    Abstract:

    An integrated top-down design system is presented in this paper for synthesizing Clock distribution networks for application to synchronous digital systems. The timing behavior of a synchronous digital circuit is obtained from the register transfer level description of the circuit, and used to determine a non-zero Clock Skew schedule which reduces the Clock period as compared to zero Skew-based approaches. Concurrently, the permissible range of Clock Skew for each local data path is calculated to determine the maximum allowed variation of the scheduled Clock Skew such that no synchronization failures occur. The choice of Clock Skew values considers several design objectives, such as minimizing the effects of process parameter variations, imposing a zero Clock Skew constraint among the input and output registers, and constraining the permissible range of each local data path to a minimum value. The Clock Skew schedule and the worst case variation of the primary process parameters are used to determine the hierarchical topology of the Clock distribution network, defining the number of levels and branches of the Clock tree and the delay associated with each branch. The delay of each branch of the Clock tree is physically implemented with distributed buffers targeted in CMOS technology using a circuit model that integrates short-channel devices with the signal waveform shape and the characteristics of the Clock tree interconnect. A bottom-up approach for calculating the worst case variation of the Clock Skew due to process parameter variations is integrated with the top-down synthesis system. Thus, the local Clock Skews and a Clock distribution network are obtained which are more tolerant to process parameter variations. This methodology and related algorithms have been demonstrated on several MCNC/ISCAS-89 benchmark circuits. Increases in system-wide Clock frequency of up to 43% as compared with zero Clock Skew implementations are shown. Furthermore, examples of Clock distribution networks that exploit intentional localized Clock Skew are presented which are tolerant to process parameter variations with worst case Clock Skew variations of up to 30%.

  • Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations
    1997
    Co-Authors: Jose L. Neves, Eby G. Friedman
    Abstract:

    An integrated top-down design system is presented in this paper for synthesizing Clock distribution networks for application to synchronous digital systems. The timing behavior of a synchronous digital circuit is obtained from the register transfer level description of the circuit, and used to determine a non-zero Clock Skew schedule which reduces the Clock period as compared to zero Skew-based approaches. Concurrently, the permissible range of Clock Skew for each local data path is calculated to determine the maximum allowed variation of the scheduled Clock Skew such that no synchronization failures occur. The choice of Clock Skew values considers several design objectives, such as minimizing the effects of process parameter variations, imposing a zero Clock Skew constraint among the input and output registers, and constraining the permissible range of each local data path to a minimum value. The Clock Skew schedule and the worst case variation of the primary process parameters are used to determine the hierarchical topology of the Clock distribution network, defining the number of levels and branches of the Clock tree and the delay associated with each branch. The delay of each branch of the Clock tree is physically implemented with distributed buffers targeted in CMOS technology using a circuit model that integrates short-channel devices with the signal waveform shape and the characteristics of the Clock tree interconnect. A bottom-up approach for calculating the worst case variation of the Clock Skew due to process parameter variations is integrated with the top-down synthesis system. Thus, the local Clock Skews and a Clock distribution network are obtained which are more tolerant to process parameter variations. This methodology and related algorithms have been demonstrated on several MCNC/ISCAS-89 benchmark circuits. Increases in system-wide Clock frequency of up to 43% as compared with zero Clock Skew implementations are shown. Furthermore, examples of Clock distribution networks that exploit intentional localized Clock Skew are presented which are tolerant to process parameter variations with worst case Clock Skew variations of up to 30%.

Jianping Pan - One of the best experts on this subject based on the ideXlab platform.

  • environment aware Clock Skew estimation and synchronization for wireless sensor networks
    International Conference on Computer Communications, 2012
    Co-Authors: Zhe Yang, Lin Cai, Yu Liu, Jianping Pan
    Abstract:

    Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless sensor networks (WSNs), because WSN environments are dynamic and unpredictable. To tackle this problem, how to accurately estimate Clock Skew, the inherent reason causing Clock desynchronization, is investigated. According to the measurement results, Clock Skew is a non-stationary random process highly correlated to temperature, and its measurements contain severe noises. Based on the observation, an additional information aided multi-model Kalman filter (AMKF) algorithm is proposed, which uses temperature measurements to assist Clock Skew estimation. Using AMKF, an environment-aware Clock synchronization (EACS) scheme is proposed to dynamically compensate Clock Skew. The scheme is simple, scalable, and of low computation and energy cost. Using EACS as an additional component of the conventional synchronization protocols, the Clock is updated with local information before the Clock re-synchronization process is triggered, so it can substantially prolong the re-synchronization period, which not only reduces the energy consumption but also is essential for the scenarios where frequent synchronization is infeasible. The theoretical lower bound of Clock Skew estimation error is derived as a benchmark. Extensive simulation and experimental verification results have demonstrated the feasibility and effectiveness of the proposed scheme which can prolong the time resynchronization period by an order of magnitude in dynamic environments.

  • INFOCOM - Environment-aware Clock Skew estimation and synchronization for wireless sensor networks
    2012 Proceedings IEEE INFOCOM, 2012
    Co-Authors: Zhe Yang, Lin Cai, Yu Liu, Jianping Pan
    Abstract:

    Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless sensor networks (WSNs), because WSN environments are dynamic and unpredictable. To tackle this problem, how to accurately estimate Clock Skew, the inherent reason causing Clock desynchronization, is investigated. According to the measurement results, Clock Skew is a non-stationary random process highly correlated to temperature, and its measurements contain severe noises. Based on the observation, an additional information aided multi-model Kalman filter (AMKF) algorithm is proposed, which uses temperature measurements to assist Clock Skew estimation. Using AMKF, an environment-aware Clock synchronization (EACS) scheme is proposed to dynamically compensate Clock Skew. The scheme is simple, scalable, and of low computation and energy cost. Using EACS as an additional component of the conventional synchronization protocols, the Clock is updated with local information before the Clock re-synchronization process is triggered, so it can substantially prolong the re-synchronization period, which not only reduces the energy consumption but also is essential for the scenarios where frequent synchronization is infeasible. The theoretical lower bound of Clock Skew estimation error is derived as a benchmark. Extensive simulation and experimental verification results have demonstrated the feasibility and effectiveness of the proposed scheme which can prolong the time resynchronization period by an order of magnitude in dynamic environments.

  • adaptive Clock Skew estimation with interactive multi model kalman filters for sensor networks
    International Conference on Communications, 2010
    Co-Authors: Zhe Yang, Jianping Pan, Lin Cai
    Abstract:

    Clock synchronization is a fundamental issue in communication networks and distributed systems, and Clock Skew is the inherent cause for Clock desynchronization. Clock Skew estimation is essential to improve the efficiency and reduce the overhead of Clock synchronization schemes, and it is especially beneficial for resource-constrained devices such as sensor nodes in dynamic environments. According to the measurement, Clock Skew is environment sensitive, and no existing Clock Skew estimation schemes can accurately capture such dynamic behaviors. In this paper, we investigate a general Clock synchronization problem with variable Clock Skews and propose a new Skew estimation model based on a hybrid approach to characterizing the dynamic of Clock Skews. To estimate the time-varying Clock state vector, we employ the Interactive Multi-Model (IMM) Kalman filter, which can make soft decisions by combining results from different models. Extensive simulations have been conducted to demonstrate the effectiveness of the proposed adaptive Clock Skew estimation algorithm, which achieves a better performance with moderate computational complexity.

  • ICC - Adaptive Clock Skew Estimation with Interactive Multi-Model Kalman Filters for Sensor Networks
    2010 IEEE International Conference on Communications, 2010
    Co-Authors: Zhe Yang, Jianping Pan, Lin Cai
    Abstract:

    Clock synchronization is a fundamental issue in communication networks and distributed systems, and Clock Skew is the inherent cause for Clock desynchronization. Clock Skew estimation is essential to improve the efficiency and reduce the overhead of Clock synchronization schemes, and it is especially beneficial for resource-constrained devices such as sensor nodes in dynamic environments. According to the measurement, Clock Skew is environment sensitive, and no existing Clock Skew estimation schemes can accurately capture such dynamic behaviors. In this paper, we investigate a general Clock synchronization problem with variable Clock Skews and propose a new Skew estimation model based on a hybrid approach to characterizing the dynamic of Clock Skews. To estimate the time-varying Clock state vector, we employ the Interactive Multi-Model (IMM) Kalman filter, which can make soft decisions by combining results from different models. Extensive simulations have been conducted to demonstrate the effectiveness of the proposed adaptive Clock Skew estimation algorithm, which achieves a better performance with moderate computational complexity.

Zhe Yang - One of the best experts on this subject based on the ideXlab platform.

  • Dynamic Clock Skew Estimation and Fusion Acquainted with Environmental Factors
    Journal of Nanoelectronics and Optoelectronics, 2020
    Co-Authors: Yuquan Shu, Zhengyan Zhu, Zhe Yang, Haitao Wei, Yachuan Bao
    Abstract:

    Clock Skew reflects the drift rate of a Clock w.r.t. the nominal or reference Clock frequency, which is the root cause of Clock drifting. However, as the output of Clock is largely affected by some environmental factors. Therefore, Clock Skew estimation is particularly difficult in wireless sensor networks (WSNs), as the working environments of WSN are usually dynamic, unpredictable or even hazard. Besides, sensors are usually powered by batteries with limited communication and computation capacity. The Clock Skew is found to be non-stationary containing severe measurement and process noises. Thus, we attempt to jointly consider the environmental factors into the Clock Skew estimation using Kalman filter. We propose to use the change of temperature and/or voltage to enhance the Clock Skew estimation performance. Besides, in multi-hop wireless networks, where the synchronization is done in a hierarchical procedure, one node may have the chance to receive more than one timestamps. Therefore, we propose to use the information fusion technique to dynamically combine the information contained in different timestamps to promote the Clock Skew estimation accuracy. Besides, we further derive the statistic lower bound of estimation errors, which can serve as a benchmark. The performance of the proposed schemes have been verified by extensive simulation results, where the root mean square error (RMSE) can be reduced by around 60% when compared with the previous solutions.

  • environment aware Clock Skew estimation and synchronization for wireless sensor networks
    International Conference on Computer Communications, 2012
    Co-Authors: Zhe Yang, Lin Cai, Yu Liu, Jianping Pan
    Abstract:

    Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless sensor networks (WSNs), because WSN environments are dynamic and unpredictable. To tackle this problem, how to accurately estimate Clock Skew, the inherent reason causing Clock desynchronization, is investigated. According to the measurement results, Clock Skew is a non-stationary random process highly correlated to temperature, and its measurements contain severe noises. Based on the observation, an additional information aided multi-model Kalman filter (AMKF) algorithm is proposed, which uses temperature measurements to assist Clock Skew estimation. Using AMKF, an environment-aware Clock synchronization (EACS) scheme is proposed to dynamically compensate Clock Skew. The scheme is simple, scalable, and of low computation and energy cost. Using EACS as an additional component of the conventional synchronization protocols, the Clock is updated with local information before the Clock re-synchronization process is triggered, so it can substantially prolong the re-synchronization period, which not only reduces the energy consumption but also is essential for the scenarios where frequent synchronization is infeasible. The theoretical lower bound of Clock Skew estimation error is derived as a benchmark. Extensive simulation and experimental verification results have demonstrated the feasibility and effectiveness of the proposed scheme which can prolong the time resynchronization period by an order of magnitude in dynamic environments.

  • INFOCOM - Environment-aware Clock Skew estimation and synchronization for wireless sensor networks
    2012 Proceedings IEEE INFOCOM, 2012
    Co-Authors: Zhe Yang, Lin Cai, Yu Liu, Jianping Pan
    Abstract:

    Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless sensor networks (WSNs), because WSN environments are dynamic and unpredictable. To tackle this problem, how to accurately estimate Clock Skew, the inherent reason causing Clock desynchronization, is investigated. According to the measurement results, Clock Skew is a non-stationary random process highly correlated to temperature, and its measurements contain severe noises. Based on the observation, an additional information aided multi-model Kalman filter (AMKF) algorithm is proposed, which uses temperature measurements to assist Clock Skew estimation. Using AMKF, an environment-aware Clock synchronization (EACS) scheme is proposed to dynamically compensate Clock Skew. The scheme is simple, scalable, and of low computation and energy cost. Using EACS as an additional component of the conventional synchronization protocols, the Clock is updated with local information before the Clock re-synchronization process is triggered, so it can substantially prolong the re-synchronization period, which not only reduces the energy consumption but also is essential for the scenarios where frequent synchronization is infeasible. The theoretical lower bound of Clock Skew estimation error is derived as a benchmark. Extensive simulation and experimental verification results have demonstrated the feasibility and effectiveness of the proposed scheme which can prolong the time resynchronization period by an order of magnitude in dynamic environments.

  • adaptive Clock Skew estimation with interactive multi model kalman filters for sensor networks
    International Conference on Communications, 2010
    Co-Authors: Zhe Yang, Jianping Pan, Lin Cai
    Abstract:

    Clock synchronization is a fundamental issue in communication networks and distributed systems, and Clock Skew is the inherent cause for Clock desynchronization. Clock Skew estimation is essential to improve the efficiency and reduce the overhead of Clock synchronization schemes, and it is especially beneficial for resource-constrained devices such as sensor nodes in dynamic environments. According to the measurement, Clock Skew is environment sensitive, and no existing Clock Skew estimation schemes can accurately capture such dynamic behaviors. In this paper, we investigate a general Clock synchronization problem with variable Clock Skews and propose a new Skew estimation model based on a hybrid approach to characterizing the dynamic of Clock Skews. To estimate the time-varying Clock state vector, we employ the Interactive Multi-Model (IMM) Kalman filter, which can make soft decisions by combining results from different models. Extensive simulations have been conducted to demonstrate the effectiveness of the proposed adaptive Clock Skew estimation algorithm, which achieves a better performance with moderate computational complexity.

  • ICC - Adaptive Clock Skew Estimation with Interactive Multi-Model Kalman Filters for Sensor Networks
    2010 IEEE International Conference on Communications, 2010
    Co-Authors: Zhe Yang, Jianping Pan, Lin Cai
    Abstract:

    Clock synchronization is a fundamental issue in communication networks and distributed systems, and Clock Skew is the inherent cause for Clock desynchronization. Clock Skew estimation is essential to improve the efficiency and reduce the overhead of Clock synchronization schemes, and it is especially beneficial for resource-constrained devices such as sensor nodes in dynamic environments. According to the measurement, Clock Skew is environment sensitive, and no existing Clock Skew estimation schemes can accurately capture such dynamic behaviors. In this paper, we investigate a general Clock synchronization problem with variable Clock Skews and propose a new Skew estimation model based on a hybrid approach to characterizing the dynamic of Clock Skews. To estimate the time-varying Clock state vector, we employ the Interactive Multi-Model (IMM) Kalman filter, which can make soft decisions by combining results from different models. Extensive simulations have been conducted to demonstrate the effectiveness of the proposed adaptive Clock Skew estimation algorithm, which achieves a better performance with moderate computational complexity.

Andreas Zinnen - One of the best experts on this subject based on the ideXlab platform.

  • GLOBECOM - Clock Skew based remote device fingerprinting demystified
    2012 IEEE Global Communications Conference (GLOBECOM), 2012
    Co-Authors: Fabian Lanze, Andriy Panchenko, Benjamin Braatz, Andreas Zinnen
    Abstract:

    Commonly used identifiers for IEEE 802.11 access points (APs), such as network name (SSID), MAC, or IP address can be easily spoofed. This allows an attacker to fake a real AP and intercept, collect, or alter (potentially even encrypted) data. In this paper, we address the aforementioned problem by studying limits of unique remote physical device identification based on their Clock Skew—an unavoidable phenomenon that causes Clocks to run at marginal but measurably different speed. To this end, we propose an algorithm for passive fingerprinting using timestamps regularly sent by APs in beacon frames. The major advantages of our method are that it is online and that we are able to eliminate the influence of Clock Skew of the measurement device. Hence, fingerprints performed by different devices become comparable. We calculate the precision of our Clock Skew measurement algorithm and provide a termination criterion for estimation of the Clock Skew with arbitrary precision. Moreover, conducting a large scale evaluation, we study the stability and uniqueness of Clock Skew as a means for remote wireless device identification.

  • Clock Skew based remote device fingerprinting demystified
    2012 IEEE Global Communications Conference (GLOBECOM), 2012
    Co-Authors: Fabian Lanze, Andriy Panchenko, Benjamin Braatz, Andreas Zinnen
    Abstract:

    Commonly used identifiers for IEEE 802.11 access points (APs), such as network name (SSID), MAC, or IP address can be easily spoofed. This allows an attacker to fake a real AP and intercept, collect, or alter (potentially even encrypted) data. In this paper, we address the aforementioned problem by studying limits of unique remote physical device identification based on their Clock Skew - an unavoidable phenomenon that causes Clocks to run at marginal but measurably different speed. To this end, we propose an algorithm for passive fingerprinting using timestamps regularly sent by APs in beacon frames. The major advantages of our method are that it is online and that we are able to eliminate the influence of Clock Skew of the measurement device. Hence, fingerprints performed by different devices become comparable. We calculate the precision of our Clock Skew measurement algorithm and provide a termination criterion for estimation of the Clock Skew with arbitrary precision. Moreover, conducting a large scale evaluation, we study the stability and uniqueness of Clock Skew as a means for remote wireless device identification.

Massimo Poncino - One of the best experts on this subject based on the ideXlab platform.

  • Dynamic Management of Thermally-Induced Clock Skew : An Implementation Perspective
    Lecture Notes in Computer Science, 2006
    Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Abstract:

    High performance VLSI designs require strict control over Clock Skew since Skew directly impacts the cycle time calculation. For nano-meter CMOS designs, Clock-Skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the Clock Skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for Clock Skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve Skew issues, and have usually regarded the implementation of the thermal management scheme as a secondary problem. In this work we focus on the implementation issues involved in the implementation of a thermal management unit (TMU) relative to a Skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology and compare different implementation styles, showing that the most efficient TMU can he implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37%. in via-number).

  • PATMOS - Dynamic management of thermally-induced Clock Skew: an implementation perspective
    Lecture Notes in Computer Science, 2006
    Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Abstract:

    High performance VLSI designs require strict control over Clock Skew since Skew directly impacts the cycle time calculation. For nano-meter CMOS designs, Clock-Skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the Clock Skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for Clock Skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve Skew issues, and have usually regarded the implementation of the thermal management scheme as a secondary problem. In this work we focus on the implementation issues involved in the implementation of a thermal management unit (TMU) relative to a Skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology, and compare different implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).