The Experts below are selected from a list of 114 Experts worldwide ranked by ideXlab platform
Yang-kyu Choi - One of the best experts on this subject based on the ideXlab platform.
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FinFACT—Fin Flip-Flop Actuated Channel Transistor
2016Co-Authors: Jin-woo Han, Jae-hyuk Ahn, Yang-kyu ChoiAbstract:for a Complementary metal–oxide–semiconductor Device to pro-vide a novel function. Based on an independently controlled double-gate FinFET, the fin of the proposed transistor is sus-pended by replacing the solid-state gate dielectric with a gas-state gate dielectric, which enables flip-flop actuation of the fin. Flip-flop actuation of the fin is accomplished via electrostatic force from two separated gates, representing a binary mechanical state of the fin. It is anticipated that the virtues of the reported Device can be exploited in transformable circuit units and digital memory transistors. Index Terms—Complementary metal–oxide–semiconductor, Fin Flip-flop Actuated Channel Transistor (FinFACT), indepen-dently controlled double-gate FinFET, nanoelectromechanical system (NEMS). I
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FinFACT—Fin Flip-Flop Actuated Channel Transistor
IEEE Electron Device Letters, 2010Co-Authors: Jin-woo Han, Jae-hyuk Ahn, Yang-kyu ChoiAbstract:Nanoelectromechanical system technology is applied for a Complementary Metal-Oxide-Semiconductor Device to provide a novel function. Based on an independently controlled double-gate FinFET, the fin of the proposed transistor is suspended by replacing the solid-state gate dielectric with a gas-state gate dielectric, which enables flip-flop actuation of the fin. Flip-flop actuation of the fin is accomplished via electrostatic force from two separated gates, representing a binary mechanical state of the fin. It is anticipated that the virtues of the reported Device can be exploited in transformable circuit units and digital memory transistors.
Jin-woo Han - One of the best experts on this subject based on the ideXlab platform.
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FinFACT—Fin Flip-Flop Actuated Channel Transistor
2016Co-Authors: Jin-woo Han, Jae-hyuk Ahn, Yang-kyu ChoiAbstract:for a Complementary metal–oxide–semiconductor Device to pro-vide a novel function. Based on an independently controlled double-gate FinFET, the fin of the proposed transistor is sus-pended by replacing the solid-state gate dielectric with a gas-state gate dielectric, which enables flip-flop actuation of the fin. Flip-flop actuation of the fin is accomplished via electrostatic force from two separated gates, representing a binary mechanical state of the fin. It is anticipated that the virtues of the reported Device can be exploited in transformable circuit units and digital memory transistors. Index Terms—Complementary metal–oxide–semiconductor, Fin Flip-flop Actuated Channel Transistor (FinFACT), indepen-dently controlled double-gate FinFET, nanoelectromechanical system (NEMS). I
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FinFACT—Fin Flip-Flop Actuated Channel Transistor
IEEE Electron Device Letters, 2010Co-Authors: Jin-woo Han, Jae-hyuk Ahn, Yang-kyu ChoiAbstract:Nanoelectromechanical system technology is applied for a Complementary Metal-Oxide-Semiconductor Device to provide a novel function. Based on an independently controlled double-gate FinFET, the fin of the proposed transistor is suspended by replacing the solid-state gate dielectric with a gas-state gate dielectric, which enables flip-flop actuation of the fin. Flip-flop actuation of the fin is accomplished via electrostatic force from two separated gates, representing a binary mechanical state of the fin. It is anticipated that the virtues of the reported Device can be exploited in transformable circuit units and digital memory transistors.
Akira Toriumi - One of the best experts on this subject based on the ideXlab platform.
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negative differential conductance at room temperature in three terminal silicon surface junction tunneling Device
Applied Physics Letters, 1997Co-Authors: Junji Koga, Akira ToriumiAbstract:Negative differential conductance based on forward biased band-to-band tunneling is demonstrated at room temperature in a three-terminal silicon surface junction tunneling Device. The Device is fabricated on silicon dioxide to achieve an extremely small bulk leakage current together with a sharp drain impurity profile. A new Device structure, in which the active tunneling junction is away from the field isolation, is also employed to totally eliminate excess tunneling current at the field oxide corner. It is observed that the tunneling current is largely controlled by the gate bias which modulates the tunneling distance. This functional Device can be easily implemented into the fabrication process for silicon ultralarge scale integrated circuits, and is expected to be a useful post Complementary metal–oxide–semiconductor Device in future silicon technology.
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negative differential conductance in three terminal silicon tunneling Device
Applied Physics Letters, 1996Co-Authors: Junji Koga, Akira ToriumiAbstract:Negative differential conductance based on lateral band‐to‐band tunneling is demonstrated in a three‐terminal silicon tunneling Device. The Device is fabricated with the current silicon ultra‐large scale integration (Si ULSI) process, taking care of the field isolation to reduce the excess tunneling current that flows over some intermediate states. It is observed that the forward biased band‐to‐band tunneling current is largely controlled by the gate bias which modulates the tunneling barrier width. The three‐terminal Si tunneling Device is promising as the post Complementary metal–oxide‐semiconductor Device in future Si ULSI.
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Negative differential conductance in three‐terminal silicon tunneling Device
Applied Physics Letters, 1996Co-Authors: Junji Koga, Akira ToriumiAbstract:Negative differential conductance based on lateral band‐to‐band tunneling is demonstrated in a three‐terminal silicon tunneling Device. The Device is fabricated with the current silicon ultra‐large scale integration (Si ULSI) process, taking care of the field isolation to reduce the excess tunneling current that flows over some intermediate states. It is observed that the forward biased band‐to‐band tunneling current is largely controlled by the gate bias which modulates the tunneling barrier width. The three‐terminal Si tunneling Device is promising as the post Complementary metal–oxide‐semiconductor Device in future Si ULSI.
Jae-hyuk Ahn - One of the best experts on this subject based on the ideXlab platform.
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FinFACT—Fin Flip-Flop Actuated Channel Transistor
2016Co-Authors: Jin-woo Han, Jae-hyuk Ahn, Yang-kyu ChoiAbstract:for a Complementary metal–oxide–semiconductor Device to pro-vide a novel function. Based on an independently controlled double-gate FinFET, the fin of the proposed transistor is sus-pended by replacing the solid-state gate dielectric with a gas-state gate dielectric, which enables flip-flop actuation of the fin. Flip-flop actuation of the fin is accomplished via electrostatic force from two separated gates, representing a binary mechanical state of the fin. It is anticipated that the virtues of the reported Device can be exploited in transformable circuit units and digital memory transistors. Index Terms—Complementary metal–oxide–semiconductor, Fin Flip-flop Actuated Channel Transistor (FinFACT), indepen-dently controlled double-gate FinFET, nanoelectromechanical system (NEMS). I
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FinFACT—Fin Flip-Flop Actuated Channel Transistor
IEEE Electron Device Letters, 2010Co-Authors: Jin-woo Han, Jae-hyuk Ahn, Yang-kyu ChoiAbstract:Nanoelectromechanical system technology is applied for a Complementary Metal-Oxide-Semiconductor Device to provide a novel function. Based on an independently controlled double-gate FinFET, the fin of the proposed transistor is suspended by replacing the solid-state gate dielectric with a gas-state gate dielectric, which enables flip-flop actuation of the fin. Flip-flop actuation of the fin is accomplished via electrostatic force from two separated gates, representing a binary mechanical state of the fin. It is anticipated that the virtues of the reported Device can be exploited in transformable circuit units and digital memory transistors.
Zhonghou Cai - One of the best experts on this subject based on the ideXlab platform.
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strain measured in a silicon on insulator Complementary metal oxide semiconductor Device channel induced by embedded silicon carbon source drain regions
Applied Physics Letters, 2009Co-Authors: Conal E. Murray, Z Ren, A Ying, S M Polvino, I C Noyan, Zhonghou CaiAbstract:The strain imparted to 60 nm wide, silicon-on-insulator (SOI) channel regions by heteroepitaxially deposited, embedded silicon-carbon (e-SiC) features was measured using x-ray microbeam diffraction, representing one of the first direct measurements of the lattice parameter conducted in situ in an SOI Device channel. Comparisons of closed-form, analytical modeling to the measured, depth-averaged strain distributions show close correspondence for the e-SiC features but 95% of the predicted strain in the SOI channel. Mechanical constraint due to the overlying gate and the contribution of SOI underneath the e-SiC in the diffracting volume to the measurements can explain this difference.
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Strain measured in a silicon-on-insulator, Complementary Metal-Oxide-Semiconductor Device channel induced by embedded silicon-carbon source/drain regions
Applied Physics Letters, 2009Co-Authors: Conal E. Murray, Z Ren, S M Polvino, I C Noyan, A. J. Ying, Zhonghou CaiAbstract:The strain imparted to 60 nm wide, silicon-on-insulator (SOI) channel regions by heteroepitaxially deposited, embedded silicon-carbon (e-SiC) features was measured using x-ray microbeam diffraction, representing one of the first direct measurements of the lattice parameter conducted in situ in an SOI Device channel. Comparisons of closed-form, analytical modeling to the measured, depth-averaged strain distributions show close correspondence for the e-SiC features but 95% of the predicted strain in the SOI channel. Mechanical constraint due to the overlying gate and the contribution of SOI underneath the e-SiC in the diffracting volume to the measurements can explain this difference.