The Experts below are selected from a list of 44130 Experts worldwide ranked by ideXlab platform
Henry Baltes - One of the best experts on this subject based on the ideXlab platform.
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A Complementary-Metal-Oxide-Semiconductor-field-effect-transistor-compatible atomic force microscopy tip fabrication process and integrated atomic force microscopy cantilevers fabricated with this process.
Ultramicroscopy, 2002Co-Authors: Mizuki Ono, Dirk Lange, Oliver Brand, Christoph Hagleitner, Henry BaltesAbstract:A Complementary-Metal-Oxide-Semiconductor-field-effect-transistor-compatible process for the fabrication of atomic force microscopy cantilevers with integrated tips has been developed. For the first time, the tips are fabricated after the completion of the regular Complementary Metal-Oxide-Semiconductor-field-effect-transistor fabrication process sequence. On-chip circuit components, such as piezoresistive deflection sensors, deflection actuators, and amplifiers, are fabricated on the mirror-polished surface of the wafer, ensuring optimal performance. The tip fabrication process is based on anisotropic silicon etching at low temperature using a tetramethylammonium hydroxide solution. The anisotropic etching process has been optimized to ensure process controllability. Using the described process, Complementary-Metal-Oxide-Semiconductor-field-effect-transistor-based cantilevers with piezoresistive deflection sensors and integrated tips have been successfully fabricated. Force-distance curves and scanning images in constant-force mode have been recorded.
Jeffrey A. Kash - One of the best experts on this subject based on the ideXlab platform.
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Picosecond hot electron light emission from submicron Complementary metal–oxide–semiconductor circuits
Applied Physics Letters, 1997Co-Authors: J. C. Tsang, Jeffrey A. KashAbstract:Optical emission consisting of pulses with temporal widths of less than 270 ps has been detected from fully functional silicon integrated circuits fabricated using submicron Complementary metal– oxide–semiconductor (CMOS) logic gates. Emission is observed under normal bias conditions and occurs when the gates are switching. The emission arises from the hot electron populations created by the transient current pulses present in the transistors during switching. The speed and spectral characteristics of the emission suggest future applications in the measurement of timing in high speed CMOS circuits.
Byung Jin Cho - One of the best experts on this subject based on the ideXlab platform.
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Hybrid Integration of Graphene Analog and Silicon Complementary Metal–Oxide–Semiconductor Digital Circuits
ACS nano, 2016Co-Authors: Seul Ki Hong, Choong Sun Kim, Wan Sik Hwang, Byung Jin ChoAbstract:We demonstrate a hybrid integration of a graphene-based analog circuit and a silicon-based digital circuit in order to exploit the strengths of both graphene and silicon devices. This mixed signal circuit integration was achieved using a three-dimensional (3-D) integration technique where a graphene FET multimode phase shifter is fabricated on top of a silicon Complementary Metal-Oxide-Semiconductor field-effect transistor (CMOS FET) ring oscillator. The process integration scheme presented here is compatible with the conventional silicon CMOS process, and thus the graphene circuit can successfully be integrated on current semiconductor technology platforms for various applications. This 3-D integration technique allows us to take advantage of graphene's excellent inherent properties and the maturity of current silicon CMOS technology for future electronics.
Rick L. Wise - One of the best experts on this subject based on the ideXlab platform.
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Probing nanoscale local lattice strains in advanced Si Complementary Metal-Oxide-Semiconductor devices
Applied Physics Letters, 2006Co-Authors: Jie Huang, Moon J. Kim, P.r. Chidambaram, R.b. Irwin, P.j. Jones, J.w. Weijtmans, Elisabeth Marley Koontz, Y. G. Wang, S. Tang, Rick L. WiseAbstract:Local lattice strains in nanoscale Si Complementary Metal-Oxide-Semiconductor (MOS) transistors are directly measured by convergent beam electron diffraction (CBED). Through both high spatial resolution and high strain sensitivity of the CBED technique, compressive strains on the order of 10−3 from a p-type MOS transistor with a sub-100nm gate length are detected. One-dimensional quantitative strain mapping is demonstrated. The tensile strains from a ⟨100⟩ channel n-type MOS transistor are observed at the ⟨910⟩ zone axis. It is found that the strain increases with the thickness of the silicon nitride-capping layer, which is consistent with the device’s electrical behavior.
Paul C. Jamison - One of the best experts on this subject based on the ideXlab platform.
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Precision Resistor Integration into a Submicron Silicided Complementary Metal Oxide Semiconductor Technology
Journal of The Electrochemical Society, 2000Co-Authors: Glen L. Miles, Frank Grellner, Paul C. JamisonAbstract:This paper examines the process issues of integrating a precision resistor feature into an existing salicided Complementary metal oxide semiconductor technology. The resistor features are created by selectively blocking salicide formation with a thin nitride layer that must be compatible with the existing device and salicide processes. The integrity of the blocking layer during the HF-based salicide preclean is of special concern. Methods to monitor and control the properties of the thin nitride blocking layer have been developed.