The Experts below are selected from a list of 213 Experts worldwide ranked by ideXlab platform
T Van Duzer - One of the best experts on this subject based on the ideXlab platform.
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High-speed demonstration of a superconducting pseudo-random bit-sequence generator
IEEE Transactions on Applied Superconductivity, 2000Co-Authors: Z. Wang, W.j. Perold, M.j. Jeffery, T Van DuzerAbstract:This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with Complementary Output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.
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RSFQ multiplexer and demultiplexer
IEEE Transactions on Applied Superconductivity, 1999Co-Authors: L. Zheng, N. Yoshikawa, J. Deng, X. Meng, S. Whiteley, T Van DuzerAbstract:An 1:8 RSFQ demultiplexer (DEMUX) and an 8:1 RSFQ multiplexer (MUX) were designed, simulated and optimized to operate at about 20 GHz. Both the inputs and Outputs of the DEMUX are Complementary dual-rail signals. The basic 2-bit DEMUX module is a self-clocked dual-rail T flip-flop. This DEMUX has a simpler structure than an earlier version of a data-driven-self-timed (DDST) DEMUX developed in our laboratory; however its simulated dc bias margin is (-20%, +20%), which is lower than the more complex device (-29%, +29%). The MUX takes lower data rate single-rail inputs and combines them sequentially into a single Output. The Complementary Output is recovered from the Output itself to facilitate interfacing to other dual-rail circuits on chip. The calculated dc bias margin is (-30 %, +28%). Circuit functionality is verified for the 2-bit MUX and the 2-bit DEMUX at low speed. An on-chip high-speed test system is designed to evaluate operation of the MUX and DEMUX at 20 GHz. The circuits are fabricated using a 1 kA/cm/sup 2/ niobium process at both UCB and HYPRES.
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Monte Carlo optimization of superconducting Complementary Output switching logic circuits
IEEE Transactions on Applied Superconductivity, 1998Co-Authors: Mark Jeffery, Willem Perold, Zuoqin Wang, T Van DuzerAbstract:The authors have previously proposed a new superconducting voltage-state logic family called Complementary Output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.
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Experimental demonstration of Complementary Output switching logic approaching 10 Gb/s clock frequencies
IEEE Transactions on Applied Superconductivity, 1997Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We have proposed a new type of voltage-state logic called Complementary Output Switching Logic (COSL). The COSL circuits were optimized for 5-10 GHz operation using a Monte Carlo method. Here we present experimental test results of the basic COSL gates in the frequency range 1-10 GHz, and discuss bit error rate measurements at 2-5 Gb/s.
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superconducting Complementary Output switching logic operating at 5 10 gb s
Applied Physics Letters, 1996Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We present experimental results of superconducting voltage‐state Complementary Output switching logic gates operating 10 Gb/s and 2‐bit encoder circuits clocked at 5–8 Gb/s. The logic gates and circuits were designed using a Monte Carlo optimization process so that they have a high theoretical yield at 5–10 Gb/s in spite of existing Josephson junction process variations.
Anthony L Al Lentine - One of the best experts on this subject based on the ideXlab platform.
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Low-Voltage, Compact, Depletion-Mode, Silicon
2020Co-Authors: Michael R. Watts, Douglas C. Trotter, Ralph W. Young, William A. Zortman, Anthony L Al LentineAbstract:Through rigorous process, electrical, and optical sim- ulations, we develop a new silicon depletion-mode vertical p-n junction phase-modulator implemented in Mach-Zehnder mod- ulator configuration, enabling an ultralow measured Vπ L of only ∼ 1V ·cm. Further, in a 500-µm-long lumped element device, we demonstrate a 10-Gb/s nonreturn-to-zero data transmission with wide-open Complementary Output eye diagrams without the use of signal preemphasis. Index Terms—Diodes, optical modulation, silicon.
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Low-voltage, compact, depletion-mode, silicon MachZehnder modulator
IEEE Journal on Selected Topics in Quantum Electronics, 2010Co-Authors: Michael R. Watts, Douglas C. Trotter, Ralph W. Young, William A. Zortman, Anthony L Al LentineAbstract:Through rigorous process, electrical, and optical simulations, we develop a new silicon depletion-mode vertical p-n junction phase-modulator implemented in Mach-Zehnder modulator configuration, enabling an ultralow measured V ?? L of only ~ 1 V??cm. Further, in a 500-??m-long lumped element device, we demonstrate a 10-Gb/s nonreturn-to-zero data transmission with wide-open Complementary Output eye diagrams without the use of signal preemphasis.
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Low-Voltage, Vertical-Junction, Depletion-Mode, Silicon Mach-Zehnder Modulator with Complementary Outputs
Advances in Optical Sciences Congress, 2009Co-Authors: Michael R. Watts, Douglas C. Trotter, Ralph W. Young, William A. Zortman, Anthony L Al LentineAbstract:We demonstrate a new silicon depletion-mode vertical p-n junction phase-modulator implemented in a lumped-element Mach-Zehnder modulator configuration enabling an ultra-low V?L of ~1V·cm and 10Gb/s non-return-to-zero (NRZ) data transmission with wide-open Complementary Output eye diagrams.
Willem Perold - One of the best experts on this subject based on the ideXlab platform.
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Complementary Output switching logic: a superconducting voltage-state logic family operating at microwave frequencies
Proceedings of the 1998 South African Symposium on Communications and Signal Processing-COMSIG '98 (Cat. No. 98EX214), 1998Co-Authors: Willem PeroldAbstract:The development of a new superconducting logic family, Complementary Output switching logic (COSL), is described. It is described how the two main problems inhibiting superconducting operation at microwave frequencies, namely magnetic flux trapping and large variations of the nominal component values due to the fabrication process, are solved. A brief overview of the operation of the basic logic gate and the layout process is given. Measured results of the basic gates are given for frequencies up to 18 GHz. The measured results of more complex circuits, such as a code converter and a pseudo-random bit sequence generator, are also presented.
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Monte Carlo optimization of superconducting Complementary Output switching logic circuits
IEEE Transactions on Applied Superconductivity, 1998Co-Authors: Mark Jeffery, Willem Perold, Zuoqin Wang, T Van DuzerAbstract:The authors have previously proposed a new superconducting voltage-state logic family called Complementary Output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.
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Experimental demonstration of Complementary Output switching logic approaching 10 Gb/s clock frequencies
IEEE Transactions on Applied Superconductivity, 1997Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We have proposed a new type of voltage-state logic called Complementary Output Switching Logic (COSL). The COSL circuits were optimized for 5-10 GHz operation using a Monte Carlo method. Here we present experimental test results of the basic COSL gates in the frequency range 1-10 GHz, and discuss bit error rate measurements at 2-5 Gb/s.
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superconducting Complementary Output switching logic operating at 5 10 gb s
Applied Physics Letters, 1996Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We present experimental results of superconducting voltage‐state Complementary Output switching logic gates operating 10 Gb/s and 2‐bit encoder circuits clocked at 5–8 Gb/s. The logic gates and circuits were designed using a Monte Carlo optimization process so that they have a high theoretical yield at 5–10 Gb/s in spite of existing Josephson junction process variations.
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Superconducting Complementary Output switching logic operating at 5–10 Gb/s
Applied Physics Letters, 1996Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We present experimental results of superconducting voltage‐state Complementary Output switching logic gates operating 10 Gb/s and 2‐bit encoder circuits clocked at 5–8 Gb/s. The logic gates and circuits were designed using a Monte Carlo optimization process so that they have a high theoretical yield at 5–10 Gb/s in spite of existing Josephson junction process variations.
Mark Jeffery - One of the best experts on this subject based on the ideXlab platform.
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Monte Carlo optimization of superconducting Complementary Output switching logic circuits
IEEE Transactions on Applied Superconductivity, 1998Co-Authors: Mark Jeffery, Willem Perold, Zuoqin Wang, T Van DuzerAbstract:The authors have previously proposed a new superconducting voltage-state logic family called Complementary Output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.
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Experimental demonstration of Complementary Output switching logic approaching 10 Gb/s clock frequencies
IEEE Transactions on Applied Superconductivity, 1997Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We have proposed a new type of voltage-state logic called Complementary Output Switching Logic (COSL). The COSL circuits were optimized for 5-10 GHz operation using a Monte Carlo method. Here we present experimental test results of the basic COSL gates in the frequency range 1-10 GHz, and discuss bit error rate measurements at 2-5 Gb/s.
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superconducting Complementary Output switching logic operating at 5 10 gb s
Applied Physics Letters, 1996Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We present experimental results of superconducting voltage‐state Complementary Output switching logic gates operating 10 Gb/s and 2‐bit encoder circuits clocked at 5–8 Gb/s. The logic gates and circuits were designed using a Monte Carlo optimization process so that they have a high theoretical yield at 5–10 Gb/s in spite of existing Josephson junction process variations.
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Superconducting Complementary Output switching logic operating at 5–10 Gb/s
Applied Physics Letters, 1996Co-Authors: Mark Jeffery, Willem Perold, T Van DuzerAbstract:We present experimental results of superconducting voltage‐state Complementary Output switching logic gates operating 10 Gb/s and 2‐bit encoder circuits clocked at 5–8 Gb/s. The logic gates and circuits were designed using a Monte Carlo optimization process so that they have a high theoretical yield at 5–10 Gb/s in spite of existing Josephson junction process variations.
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Complementary Output switching logic-a new superconducting voltage-state logic family
IEEE Transactions on Applied Superconductivity, 1996Co-Authors: Willem Perold, Mark Jeffery, Zuoqin Wang, T Van DuzerAbstract:A new superconducting logic family, Complementary Output switching logic (COSL), is proposed. The family consists of AND, NAND, OR, NOR, and XOR gates. The performance of the gates is predicted with a procedure that evaluates the dynamic performance when all circuit parameters are randomly varied around the nominal values. The simulated performance of the gates is compared with modified variable threshold logic (MVTL) at 5 GHz and 10 GHz. The functionality and margins of the COSL gates are verified by measurements at low speed.
Michael R. Watts - One of the best experts on this subject based on the ideXlab platform.
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Low-Voltage, Compact, Depletion-Mode, Silicon
2020Co-Authors: Michael R. Watts, Douglas C. Trotter, Ralph W. Young, William A. Zortman, Anthony L Al LentineAbstract:Through rigorous process, electrical, and optical sim- ulations, we develop a new silicon depletion-mode vertical p-n junction phase-modulator implemented in Mach-Zehnder mod- ulator configuration, enabling an ultralow measured Vπ L of only ∼ 1V ·cm. Further, in a 500-µm-long lumped element device, we demonstrate a 10-Gb/s nonreturn-to-zero data transmission with wide-open Complementary Output eye diagrams without the use of signal preemphasis. Index Terms—Diodes, optical modulation, silicon.
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Low-voltage, compact, depletion-mode, silicon MachZehnder modulator
IEEE Journal on Selected Topics in Quantum Electronics, 2010Co-Authors: Michael R. Watts, Douglas C. Trotter, Ralph W. Young, William A. Zortman, Anthony L Al LentineAbstract:Through rigorous process, electrical, and optical simulations, we develop a new silicon depletion-mode vertical p-n junction phase-modulator implemented in Mach-Zehnder modulator configuration, enabling an ultralow measured V ?? L of only ~ 1 V??cm. Further, in a 500-??m-long lumped element device, we demonstrate a 10-Gb/s nonreturn-to-zero data transmission with wide-open Complementary Output eye diagrams without the use of signal preemphasis.
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Low-Voltage, Vertical-Junction, Depletion-Mode, Silicon Mach-Zehnder Modulator with Complementary Outputs
Advances in Optical Sciences Congress, 2009Co-Authors: Michael R. Watts, Douglas C. Trotter, Ralph W. Young, William A. Zortman, Anthony L Al LentineAbstract:We demonstrate a new silicon depletion-mode vertical p-n junction phase-modulator implemented in a lumped-element Mach-Zehnder modulator configuration enabling an ultra-low V?L of ~1V·cm and 10Gb/s non-return-to-zero (NRZ) data transmission with wide-open Complementary Output eye diagrams.