The Experts below are selected from a list of 315 Experts worldwide ranked by ideXlab platform
Nail Etkin Can Akkaya - One of the best experts on this subject based on the ideXlab platform.
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a compact energy efficient pseudo static camouflaged Logic Family
Hardware-Oriented Security and Trust, 2018Co-Authors: Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken MaiAbstract:Protecting hardware IP from reverse engineering threats is becoming increasingly challenging with advances in reverse engineering techniques. Different camouflaged Logic families based on multi-Vt transistors have been recently proposed to combat reverse engineering threats. While multi-Vt based camouflaged Logic gates offer cells that have an identical layout with multiple functionalities, they typically incur significant overheads in power, area, and delay. Moreover, amplifying the threshold voltage difference to Logic levels while maintaining the noise margins needs careful analysis of PVT variations and mismatch. In this paper, a Pseudo-Static Camouflaged (PS-CAMO) Logic Family is proposed to improve the energy overheads of camouflaged Logic gates while maintaining the reliability and yields of static CMOS Logic gates. Post-layout simulations of a high-performance fully camouflaged S-box in a 65nm industrial CMOS process shows a 42% reduction in energy and a 26% reduction in area compared to a previously proposed Threshold Voltage Defined (TVD) camouflaged Logic Family.
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HOST - A compact energy-efficient pseudo-static camouflaged Logic Family
2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018Co-Authors: Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken MaiAbstract:Protecting hardware IP from reverse engineering threats is becoming increasingly challenging with advances in reverse engineering techniques. Different camouflaged Logic families based on multi-Vt transistors have been recently proposed to combat reverse engineering threats. While multi-Vt based camouflaged Logic gates offer cells that have an identical layout with multiple functionalities, they typically incur significant overheads in power, area, and delay. Moreover, amplifying the threshold voltage difference to Logic levels while maintaining the noise margins needs careful analysis of PVT variations and mismatch. In this paper, a Pseudo-Static Camouflaged (PS-CAMO) Logic Family is proposed to improve the energy overheads of camouflaged Logic gates while maintaining the reliability and yields of static CMOS Logic gates. Post-layout simulations of a high-performance fully camouflaged S-box in a 65nm industrial CMOS process shows a 42% reduction in energy and a 26% reduction in area compared to a previously proposed Threshold Voltage Defined (TVD) camouflaged Logic Family.
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A secure camouflaged threshold voltage defined Logic Family
2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016Co-Authors: Burak Erbagci, Cagri Erbagci, Nail Etkin Can AkkayaAbstract:A myriad of security vulnerabilites can be exposed via the reverse engineering of the integrated circuits contained in electronics systems. The goal of IC reverse engineering is to uncover the functionality and internal structure of the chip via techniques such as depackaging/delayering, high-resolution imaging, probing, and side-channel examination. With this knowledge, an attacker can more efficiently mount various attacks, clone/-counterfeit the design possibly with hardware Trojans inserted, and discover trade secrets. We propose a gate camouflaging technique that relies on the usage of different threshold voltage transistors, but with identical layouts, to determine the Logic gate function. In our threshold voltage defined (TVD) camouflaging technique, every TVD Logic gate has the same physical structure and is one time mask programmed with different threshold implants for different boolean functionality. We design and implement TVD Logic gates in an industrial 65nm bulk CMOS process. Using post-layout extracted simulation, we evaluate the Logic style for VLSI overheads (area, power, delay) versus conventional Logic, for process variablity robustness, and for various security metrics. Further, we evaluate the macro block overheads for ISCAS benchmark designs under various levels of TVD gate replacement upto and including 100% replacement. TVD Logic gates are found to be CMOS process compatible, low overhead, and to increase security against various forms of attacks.
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a dpa resistant self timed three phase dual rail pre charge Logic Family
Hardware-Oriented Security and Trust, 2015Co-Authors: Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken MaiAbstract:Differential power analysis (DPA) has been shown to be a highly effective and easy to mount side-channel attack. One effective method of increasing DPA resistance is to use three-phase dual-rail pre-charge Logic (TDPL), but this type of Logic is vulnerable to manipulation of the clock generation/distribution hardware. If an attacker can slow down the clock, separate the evaluate phase from the discharge phase, or eliminate the discharge phase entirely, the DPA resistance of TDPL is no better than a basic dynamic dual rail Logic Family. To counter such attacks, we propose a self-timed three-phase dual-rail pre-charge Logic Family (ST-TDPL), which internally generates the discharge clock in a distributed manner. Thus, an attacker cannot split the discharge phase from the evaluate phase. We compare the area, energy, and normalized energy deviation (NED) of ST-TDPL against Simple TDPL, Simple TDPL with no discharge phase, and static CMOS using an iso-performance design point (i.e., all gates have the same delay) in an industrial 65nm bulk CMOS. The results show that ST-TDPL achieves a similarly low NED value as TDPL, while also providing protection against attacks on the clocking infrastructure.
P R Deshmukh - One of the best experts on this subject based on the ideXlab platform.
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design of cmos ternary Logic Family based on single supply voltage
International Conference on Pervasive Computing, 2015Co-Authors: V T Gaikwad, P R DeshmukhAbstract:Since inception, CMOS Logic is considered for implementation of only binary Logic. As the circuit complexity is increasing, the interconnection in binary occupies large area on a VLSI chip and thus, degrading the performance of binary. Hence the non binary higher radix Logic which is called as multi valued Logic (MVL) is considered as solution to this issue. A ternary Logic or a three-valued Logic is considered as the best radix of several MVL systems. In this paper, the designs of ternary Logic circuits are proposed based on single power supply voltage. The proposed ternary Logic gates are useful in designing the ternary Logic circuits. The proposed designs are based on the use of only enhancement type MOSFETS so that it can be implemented with recent CMOS technology. The design of a set of inverters and basic ternary Logic gates is proposed. The transistor count in the basic ternary gates is being reduced thereby improving component density. The proposed GATES are designed & simulated with the help of Microwind EDA tool & can be implemented at its layout side using VLSI CMOS technology.
Burak Erbagci - One of the best experts on this subject based on the ideXlab platform.
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a compact energy efficient pseudo static camouflaged Logic Family
Hardware-Oriented Security and Trust, 2018Co-Authors: Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken MaiAbstract:Protecting hardware IP from reverse engineering threats is becoming increasingly challenging with advances in reverse engineering techniques. Different camouflaged Logic families based on multi-Vt transistors have been recently proposed to combat reverse engineering threats. While multi-Vt based camouflaged Logic gates offer cells that have an identical layout with multiple functionalities, they typically incur significant overheads in power, area, and delay. Moreover, amplifying the threshold voltage difference to Logic levels while maintaining the noise margins needs careful analysis of PVT variations and mismatch. In this paper, a Pseudo-Static Camouflaged (PS-CAMO) Logic Family is proposed to improve the energy overheads of camouflaged Logic gates while maintaining the reliability and yields of static CMOS Logic gates. Post-layout simulations of a high-performance fully camouflaged S-box in a 65nm industrial CMOS process shows a 42% reduction in energy and a 26% reduction in area compared to a previously proposed Threshold Voltage Defined (TVD) camouflaged Logic Family.
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HOST - A compact energy-efficient pseudo-static camouflaged Logic Family
2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018Co-Authors: Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken MaiAbstract:Protecting hardware IP from reverse engineering threats is becoming increasingly challenging with advances in reverse engineering techniques. Different camouflaged Logic families based on multi-Vt transistors have been recently proposed to combat reverse engineering threats. While multi-Vt based camouflaged Logic gates offer cells that have an identical layout with multiple functionalities, they typically incur significant overheads in power, area, and delay. Moreover, amplifying the threshold voltage difference to Logic levels while maintaining the noise margins needs careful analysis of PVT variations and mismatch. In this paper, a Pseudo-Static Camouflaged (PS-CAMO) Logic Family is proposed to improve the energy overheads of camouflaged Logic gates while maintaining the reliability and yields of static CMOS Logic gates. Post-layout simulations of a high-performance fully camouflaged S-box in a 65nm industrial CMOS process shows a 42% reduction in energy and a 26% reduction in area compared to a previously proposed Threshold Voltage Defined (TVD) camouflaged Logic Family.
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A secure camouflaged threshold voltage defined Logic Family
2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016Co-Authors: Burak Erbagci, Cagri Erbagci, Nail Etkin Can AkkayaAbstract:A myriad of security vulnerabilites can be exposed via the reverse engineering of the integrated circuits contained in electronics systems. The goal of IC reverse engineering is to uncover the functionality and internal structure of the chip via techniques such as depackaging/delayering, high-resolution imaging, probing, and side-channel examination. With this knowledge, an attacker can more efficiently mount various attacks, clone/-counterfeit the design possibly with hardware Trojans inserted, and discover trade secrets. We propose a gate camouflaging technique that relies on the usage of different threshold voltage transistors, but with identical layouts, to determine the Logic gate function. In our threshold voltage defined (TVD) camouflaging technique, every TVD Logic gate has the same physical structure and is one time mask programmed with different threshold implants for different boolean functionality. We design and implement TVD Logic gates in an industrial 65nm bulk CMOS process. Using post-layout extracted simulation, we evaluate the Logic style for VLSI overheads (area, power, delay) versus conventional Logic, for process variablity robustness, and for various security metrics. Further, we evaluate the macro block overheads for ISCAS benchmark designs under various levels of TVD gate replacement upto and including 100% replacement. TVD Logic gates are found to be CMOS process compatible, low overhead, and to increase security against various forms of attacks.
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a dpa resistant self timed three phase dual rail pre charge Logic Family
Hardware-Oriented Security and Trust, 2015Co-Authors: Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken MaiAbstract:Differential power analysis (DPA) has been shown to be a highly effective and easy to mount side-channel attack. One effective method of increasing DPA resistance is to use three-phase dual-rail pre-charge Logic (TDPL), but this type of Logic is vulnerable to manipulation of the clock generation/distribution hardware. If an attacker can slow down the clock, separate the evaluate phase from the discharge phase, or eliminate the discharge phase entirely, the DPA resistance of TDPL is no better than a basic dynamic dual rail Logic Family. To counter such attacks, we propose a self-timed three-phase dual-rail pre-charge Logic Family (ST-TDPL), which internally generates the discharge clock in a distributed manner. Thus, an attacker cannot split the discharge phase from the evaluate phase. We compare the area, energy, and normalized energy deviation (NED) of ST-TDPL against Simple TDPL, Simple TDPL with no discharge phase, and static CMOS using an iso-performance design point (i.e., all gates have the same delay) in an industrial 65nm bulk CMOS. The results show that ST-TDPL achieves a similarly low NED value as TDPL, while also providing protection against attacks on the clocking infrastructure.
Sung-mo Kang - One of the best experts on this subject based on the ideXlab platform.
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High-Density Memristor-CMOS Ternary Logic Family
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021Co-Authors: Xiaoyuan Wang, Zhou Pengfei, Jason K. Eshraghian, Chih-yang Lin, Ting-chang Chang, Sung-mo KangAbstract:This paper presents the first experimental demonstration of a ternary memristor-CMOS Logic Family. We systematically design, simulate and experimentally verify the primitive Logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS Logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.
V T Gaikwad - One of the best experts on this subject based on the ideXlab platform.
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design of cmos ternary Logic Family based on single supply voltage
International Conference on Pervasive Computing, 2015Co-Authors: V T Gaikwad, P R DeshmukhAbstract:Since inception, CMOS Logic is considered for implementation of only binary Logic. As the circuit complexity is increasing, the interconnection in binary occupies large area on a VLSI chip and thus, degrading the performance of binary. Hence the non binary higher radix Logic which is called as multi valued Logic (MVL) is considered as solution to this issue. A ternary Logic or a three-valued Logic is considered as the best radix of several MVL systems. In this paper, the designs of ternary Logic circuits are proposed based on single power supply voltage. The proposed ternary Logic gates are useful in designing the ternary Logic circuits. The proposed designs are based on the use of only enhancement type MOSFETS so that it can be implemented with recent CMOS technology. The design of a set of inverters and basic ternary Logic gates is proposed. The transistor count in the basic ternary gates is being reduced thereby improving component density. The proposed GATES are designed & simulated with the help of Microwind EDA tool & can be implemented at its layout side using VLSI CMOS technology.
