The Experts below are selected from a list of 87 Experts worldwide ranked by ideXlab platform

Mitsumasa Koyanagi - One of the best experts on this subject based on the ideXlab platform.

  • Heterogeneous 3-D Integration Using Self-Assembly and Electrostatic Bonding
    IEEE Transactions on Components Packaging and Manufacturing Technology, 2016
    Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka
    Abstract:

    To overcome various concerns caused by scaling down the Device size in future Large Scale Integrated Circuits (LSIs), it is indispensable to introduce a new concept of heterogeneous 3-D integration in which various kinds of Device chips with different sizes, different Devices, and different materials are vertically stacked. To achieve such heterogeneous 3-D integration, a key technology of self-assembly and electrostatic bonding has been developed. Exploring new Devices for the Internet of Things, we have fabricated several kinds of heterogeneous 3-D LSIs called superchip by stacking Compound Semiconductor Device chip, photonic Device chip, and spintronic Device chip on CMOS Device chips using self-assembly and electrostatic bonding. Furthermore, a new system integration technology using a large-area substrate has been developed to reduce the cost of 2.5-D/3-D system module. A 3-D-stacked image sensor system module for automatic driving vehicle has been fabricated using this technology.

  • Heterogeneous 3D integration for Internet of Things
    2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
    Co-Authors: Mitsumasa Koyanagi
    Abstract:

    To overcome various concerns caused by scaling-down the Device size in future LSIs, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of Device chips with different size, different Devices and different materials are vertically stacked. To achieve such heterogeneous 3D integration, a key technology of self-assembly and electrostatic (SAE) bonding has been developed. Exploring new Devices for the IoT, we have fabricated several kinds of heterogeneous 3D LSIs called super-chip by stacking Compound Semiconductor Device chip, photonic Device chip and spintronic Device chip on CMOS Device chips using SAE bonding.

  • Heterogeneous 3D integration — Technology enabler toward future super-chip
    2013 IEEE International Electron Devices Meeting, 2013
    Co-Authors: Mitsumasa Koyanagi
    Abstract:

    To overcome various concerns caused by scaling-down the Device size, it is indispensable to introduce a new concept of heterogeneous 3D integration called a super-chip in which various kinds of Device chips with different size, different Devices and different materials are stacked. A key technology of self-assembly and electrostatic (SAE) temporary bonding has been developed to achieve a super-chip. Several kinds of super-chips are fabricated by stacking Compound Semiconductor Device chip, photonic Device chip and spintronic Device chip on CMOS Device chips.

Xie Yong-gu - One of the best experts on this subject based on the ideXlab platform.

W. T. Anderson - One of the best experts on this subject based on the ideXlab platform.

  • Channel temperature measurement of GaAs Devices using an atomic force microscope
    1999 GaAs Reliability Workshop. Proceedings (Cat. No.00TH8459), 1999
    Co-Authors: W. T. Anderson, J.a. Mittereder, J.a. Roussos
    Abstract:

    We have used an atomic force microscope (AFM) to measure the channel temperature of GaAs pseudomorphic high electron mobility transistors (PHEMTs) and GaAs metal-Semiconductor field effect transistors (MESFETs) by employing a temperature sensitive tip. The improvements with this method are to greatly expand the range over which the channel temperature can be measured and to improve the spatial resolution into the submicrometer range. To our knowledge, this is the first report of an accurate, quantitative measurement of the channel temperature of a Compound Semiconductor Device using an AFM.

  • Status of Compound Semiconductor Device Reliability
    NATO ASI series. Series E Applied sciences, 1990
    Co-Authors: W. T. Anderson, Aris Christou
    Abstract:

    A review is made of Compound Semiconductor Device reliability from the period 1980 to the present. Emphasis is placed on technology based on field effect transistors (FETs). Many reliability studies were made of small signal GaAs FETs in the 1970s and of GaAs power FETs in the 1980’s; a substantial reliability base exists for these Devices. However, there remains a lack of reliability data for GaAs Devices such as digital ICs, MMICs, and heterojunction transistors (HEMTs, HBTs). Future directions for high reliability lie in Device designs to reduce channel and junction temperatures, reduction in interdiffusion and ion migration between metal/Semiconductor layers and between Semiconductor layers, and in the development of high temperature stable Schottky barrier metallizations and Ohmic contacts.

Aris Christou - One of the best experts on this subject based on the ideXlab platform.

  • Rapid Thermal Processing of Contacts and Buffer Layers for Compound Semiconductor Device Technology
    Advances in Rapid Thermal and Integrated Processing, 1996
    Co-Authors: Ting Feng, Aris Christou, D. Girginoudi, Zacharias Hatzopoulos
    Abstract:

    Rapid Thermal Processing (RTP) in the Compound Semiconductor technology has had a significant impact in making such a technology reliable and manufactureable. Since 1980 [1] RTP has been applied to achieving control of doping profiles, achieving implant activation and the application of advanced metallization systems. Since 1990 [2], RTP in the form of pulsed excimer laser processing has been applied to molecular beam epitaxial growth (MBE) for the development of high resistivity buffer lasers and for achieving the heterostructures necessary for high electron mobility transistors (HEMTs). The emphasis in the present paper is to review the GaAs Device technology, the material problems and Device structures and to show that RTP has removed key material problems which were bottlenecks in achieving a fabrication process which is reliable and high yield.

  • Status of Compound Semiconductor Device Reliability
    NATO ASI series. Series E Applied sciences, 1990
    Co-Authors: W. T. Anderson, Aris Christou
    Abstract:

    A review is made of Compound Semiconductor Device reliability from the period 1980 to the present. Emphasis is placed on technology based on field effect transistors (FETs). Many reliability studies were made of small signal GaAs FETs in the 1970s and of GaAs power FETs in the 1980’s; a substantial reliability base exists for these Devices. However, there remains a lack of reliability data for GaAs Devices such as digital ICs, MMICs, and heterojunction transistors (HEMTs, HBTs). Future directions for high reliability lie in Device designs to reduce channel and junction temperatures, reduction in interdiffusion and ion migration between metal/Semiconductor layers and between Semiconductor layers, and in the development of high temperature stable Schottky barrier metallizations and Ohmic contacts.

D.h. Chow - One of the best experts on this subject based on the ideXlab platform.

  • Heterogeneous wafer-scale integration of 250nm, 300GHz InP DHBTs with a 130nm RF-CMOS technology
    2008 IEEE International Electron Devices Meeting, 2008
    Co-Authors: J.c. Li, Y. Royter, P.r. Patterson, T. Hussain, J.r. Duvall, M.c. Montes, D. Le, D.a. Hitko, M. Sokolich, D.h. Chow
    Abstract:

    The performance advantages of InP based Devices over silicon Devices are well known, but the ability to fabricate complex, high transistor count ICs is limited both by the relative immaturity of the material system and a limited commercial market. Silicon based Devices have made significant advances in Device performance, but have not yet matched Compound Semiconductor Device performance. A large commercial market, however, has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both of these technologies in order to enable a new class of high performance ICs. This work demonstrates the wafer scale integration of an advanced 250 nm, 300 GHz fT/fMAX InP DHBT technology with IBM's 130 nm RF-CMOS technology (CMRF8SF). Such integration allows the rapid adoption of more advanced CMOS and InP DHBT technology generations.