The Experts below are selected from a list of 165 Experts worldwide ranked by ideXlab platform
Myung-joong Youn - One of the best experts on this subject based on the ideXlab platform.
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Cost-Effective Zero-Voltage and Zero-Current Switching Current-Fed Energy-Recovery Display Driver for ac Plasma Display Panel
IEEE Transactions on Power Electronics, 2007Co-Authors: Sang-kyoo Han, Gun-woo Moon, Myung-joong YounAbstract:A new cost-effective zero-voltage and zero-current switching (ZVZCS) current-fed energy-recovery display driver for a plasma display panel (PDP) is proposed. It features a simpler structure, less mass, and lower cost of production. Furthermore, since all power switches are turned on or off under zero-voltage or zero-current switching, it has several favorable advantages such as an improved electromagnetic interference (EMI), low switching losses, and reduced burden on the cooling system. Particularly, since the current source built in the inductor can compensate the large gas-discharge current, main inverter switches have the reduced current stress and turn-on timing margin. Therefore, the undesirable voltage notch problem caused by the improperly Controlled Gate signal can be solved, which enables the panel to light at lower voltage such as 143 V compared with about 165 V of the prior circuit. To confirm the operation, validity, and features of the proposed circuit, experimental results from a prototype built with 6-in test PDP are presented.
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Cost Effective Zero-Voltage and Zero-Current Switching Current-Fed Energy-Recovery Display Driver for AC Plasma Display Panel
IEEE Transactions on Power Electronics, 2007Co-Authors: Gun-woo Moon, Myung-joong YounAbstract:A new cost effective zero-voltage (ZVS) and zero-current switching (ZCS) current-fed energy-recovery display driver for a plasma display panel (PDP) is proposed. It features a simpler structure, less mass, and lower cost of production. Furthermore, since all power switches are turned on or off under ZVS or ZCS, it has several favorable advantages such as an improved electromagnetic interference, low switching losses, and reduced burden on the cooling system. Particularly, since the current source built in the inductor can compensate the large gas-discharge current, main inverter switches have the reduced current stress and turn-on timing margin. Therefore, the undesirable voltage notch problem caused by the improperly Controlled Gate signal can be solved, which enables the panel to light at lower voltage such as 143 V compared with about 165 V of the prior circuit. To confirm the operation, validity, and features of the proposed circuit, experimental results from a prototype built with a 6-in test PDP are presented
Gun-woo Moon - One of the best experts on this subject based on the ideXlab platform.
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Cost-Effective Zero-Voltage and Zero-Current Switching Current-Fed Energy-Recovery Display Driver for ac Plasma Display Panel
IEEE Transactions on Power Electronics, 2007Co-Authors: Sang-kyoo Han, Gun-woo Moon, Myung-joong YounAbstract:A new cost-effective zero-voltage and zero-current switching (ZVZCS) current-fed energy-recovery display driver for a plasma display panel (PDP) is proposed. It features a simpler structure, less mass, and lower cost of production. Furthermore, since all power switches are turned on or off under zero-voltage or zero-current switching, it has several favorable advantages such as an improved electromagnetic interference (EMI), low switching losses, and reduced burden on the cooling system. Particularly, since the current source built in the inductor can compensate the large gas-discharge current, main inverter switches have the reduced current stress and turn-on timing margin. Therefore, the undesirable voltage notch problem caused by the improperly Controlled Gate signal can be solved, which enables the panel to light at lower voltage such as 143 V compared with about 165 V of the prior circuit. To confirm the operation, validity, and features of the proposed circuit, experimental results from a prototype built with 6-in test PDP are presented.
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Cost Effective Zero-Voltage and Zero-Current Switching Current-Fed Energy-Recovery Display Driver for AC Plasma Display Panel
IEEE Transactions on Power Electronics, 2007Co-Authors: Gun-woo Moon, Myung-joong YounAbstract:A new cost effective zero-voltage (ZVS) and zero-current switching (ZCS) current-fed energy-recovery display driver for a plasma display panel (PDP) is proposed. It features a simpler structure, less mass, and lower cost of production. Furthermore, since all power switches are turned on or off under ZVS or ZCS, it has several favorable advantages such as an improved electromagnetic interference, low switching losses, and reduced burden on the cooling system. Particularly, since the current source built in the inductor can compensate the large gas-discharge current, main inverter switches have the reduced current stress and turn-on timing margin. Therefore, the undesirable voltage notch problem caused by the improperly Controlled Gate signal can be solved, which enables the panel to light at lower voltage such as 143 V compared with about 165 V of the prior circuit. To confirm the operation, validity, and features of the proposed circuit, experimental results from a prototype built with a 6-in test PDP are presented
Yan Wang - One of the best experts on this subject based on the ideXlab platform.
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4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-Controlled Gate Structure
IEEE Transactions on Electron Devices, 2017Co-Authors: Xintian Zhou, Jian Zhang, Juntao Li, Yan WangAbstract:A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-Controlled Gate structure (FJB-MOS/GJB-MOS) is presented and investiGated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the Gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance ( ${V}_{\textsf {BR}}^{{\,\textsf {2}}}/{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped Gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific Gate–drain charge ${Q}_{{\:\textsf {gd,sp}}}$ and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.
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4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-Controlled Gate Structure
IEEE Transactions on Electron Devices, 2017Co-Authors: Xintian Zhou, Jian Zhang, Juntao Li, Yan WangAbstract:A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-Controlled Gate structure (FJB-MOS/GJB-MOS) is presented and investiGated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the Gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance (VBR2/RON,sp), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped Gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific Gate-drain charge Qgd,sp and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.
Chingte Chuang - One of the best experts on this subject based on the ideXlab platform.
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Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012Co-Authors: Chien-yu Hsieh, Vita Pi Ho Hu, Pin Su, Chingte ChuangAbstract:In this work, we propose three novel independently-Controlled-Gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-Gate FinFET devices with the front-Gate devices serving as the stacking devices, and the back-Gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-Gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at VCS= 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investiGate the impacts of process variations (Leff, EOT, Wfin, and Hfin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of μ/σ ratio.
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Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM
2012 IEEE Asia Pacific Conference on Circuits and Systems, 2012Co-Authors: Ming-fu Tsai, Pin Su, Jen-huan Tsai, Chingte ChuangAbstract:In this paper, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-Controlled-Gate. Extensive simulations suggest the proposed structures are robust against random offset errors. The proposed CLSA structures feature significant offset suppression capabilities with σoffset reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.
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Disturb-free Independently-Controlled-Gate 7T FinFET SRAM cell
Proceedings of 2011 International Symposium on VLSI Technology Systems and Applications, 2011Co-Authors: Yin-nien Chen, Vita Pi Ho Hu, Pin Su, Chien-yu Hsieh, Chingte ChuangAbstract:We propose a novel Independently-Controlled-Gate (IG) 7T FinFET SRAM cell. The cell utilizes the “stacking-like” property of split-Gate super-high-VT FinFET devices to eliminate Read disturb and Half-Select disturb, and keeper and VSS-control to mitiGate Read bit-line leakage. The stability and performance of the proposed cell are compared with the conventional 6T tied-Gate cell and recently reported 6T-Column-Decoupled cell using TCAD mixed-mode simulations. 3D atomistic mixed-mode Monte-Carlo simulations are performed to investiGate the impact of local random variations due to Fin LER. The results indicate that the proposed cell shows better cell stability and provides sufficient margins even considering intrinsic device variations.
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Independently-Controlled-Gate FinFET Schmitt Trigger sub-threshold SRAMs
2010 IEEE International SOI Conference (SOI), 2010Co-Authors: Chien-yu Hsieh, Vita Pi Ho Hu, Pin Su, Chingte ChuangAbstract:We propose three novel Independently-Controlled-Gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG ST 8T SRAM cells utilize split-Gate FinFET devices to provide built-in feedback mechanism for Schmitt Trigger action. 3D mixed-mode simulations are used to evaluate the RSNM, WSNM, HSNM, and Standby leakage of proposed cells. The proposed cells demonstrate 1.81X and 2.11X higher nominal RSNM at VCS=0.4V and 0.15V, respectively. The cell AC performance are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3D mixed-mode Monte Carlo simulations are performed to investiGate the impacts of process variations (Leff and Wfin) and random variations (Gate LER and Fin LER) on RSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of μ/σ ratio=7. With enhanced cell stability, reduced cell area and Standby leakage, adequate performance, and robust tolerance to process variations and random variations, these proposed cells are promising candidates for future ultra-low-voltage sub-threshold applications.
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Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM Model
IEEE Transactions on Electron Devices, 2010Co-Authors: Yusheng Wu, Vita Pi Ho Hu, Pin Su, Chingte ChuangAbstract:In this paper, the static noise margin (SNM) of FinFET static random access memory (SRAM) cells operating in the subthreshold region was investiGated using an analytical solution of 3-D Poisson's equation. An analytical SNM model for subthreshold FinFET SRAM was demonstrated and validated by 3-D technology computer-aided design (TCAD) mixed-mode simulations. When compared with bulk SRAM, the standard 6T FinFET cell showed larger nominal READ SNM (RSNM), better variability immunity, and lesser temperature sensitivity of cell stability. Furthermore, examination of the stabilities of several novel independently Controlled Gate FinFET SRAM cells by using the proposed SNM model showed significant nominal RSNM improvements in these novel cells. However, the write ability is found to be degraded, which thus becomes an important concern for certain configurations in the subthreshold region. The result obtained indicates that the READ/WRITE word line voltage control technique is more effective than transistor sizing in improving the stability and write ability of the FinFET subthreshold SRAM. Furthermore, the impacts of process-induced variations on cell stability were also assessed. When compared with RSNM, it was found that WRITE SNM is more susceptible to process variations. While 6T is not a viable candidate for subthreshold SRAM, and 8T/10T cells must be used in bulk CMOS, the present analysis established the potential of 6T FinFET cells for subthreshold SRAM applications.
Xintian Zhou - One of the best experts on this subject based on the ideXlab platform.
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4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-Controlled Gate Structure
IEEE Transactions on Electron Devices, 2017Co-Authors: Xintian Zhou, Jian Zhang, Juntao Li, Yan WangAbstract:A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-Controlled Gate structure (FJB-MOS/GJB-MOS) is presented and investiGated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the Gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance ( ${V}_{\textsf {BR}}^{{\,\textsf {2}}}/{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped Gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific Gate–drain charge ${Q}_{{\:\textsf {gd,sp}}}$ and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.
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4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-Controlled Gate Structure
IEEE Transactions on Electron Devices, 2017Co-Authors: Xintian Zhou, Jian Zhang, Juntao Li, Yan WangAbstract:A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-Controlled Gate structure (FJB-MOS/GJB-MOS) is presented and investiGated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the Gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance (VBR2/RON,sp), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped Gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific Gate-drain charge Qgd,sp and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.