The Experts below are selected from a list of 63 Experts worldwide ranked by ideXlab platform
Boris Murmann - One of the best experts on this subject based on the ideXlab platform.
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A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue Amplification
2008 IEEE Symposium on VLSI Circuits, 2008Co-Authors: J Hu, Noam Dolev, Boris MurmannAbstract:An ultra-low power pipelined ADC is realized by replacing Conventional Op-Amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter Operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
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a 9 4 bit 50 ms s 1 44 mw pipelined adc using dynamic residue Amplification
Symposium on VLSI Circuits, 2008Co-Authors: J Hu, Noam Dolev, Boris MurmannAbstract:An ultra-low power pipelined ADC is realized by replacing Conventional Op-Amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter Operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
J Hu - One of the best experts on this subject based on the ideXlab platform.
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A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue Amplification
2008 IEEE Symposium on VLSI Circuits, 2008Co-Authors: J Hu, Noam Dolev, Boris MurmannAbstract:An ultra-low power pipelined ADC is realized by replacing Conventional Op-Amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter Operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
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a 9 4 bit 50 ms s 1 44 mw pipelined adc using dynamic residue Amplification
Symposium on VLSI Circuits, 2008Co-Authors: J Hu, Noam Dolev, Boris MurmannAbstract:An ultra-low power pipelined ADC is realized by replacing Conventional Op-Amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter Operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
Noam Dolev - One of the best experts on this subject based on the ideXlab platform.
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A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue Amplification
2008 IEEE Symposium on VLSI Circuits, 2008Co-Authors: J Hu, Noam Dolev, Boris MurmannAbstract:An ultra-low power pipelined ADC is realized by replacing Conventional Op-Amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter Operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
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a 9 4 bit 50 ms s 1 44 mw pipelined adc using dynamic residue Amplification
Symposium on VLSI Circuits, 2008Co-Authors: J Hu, Noam Dolev, Boris MurmannAbstract:An ultra-low power pipelined ADC is realized by replacing Conventional Op-Amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter Operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
Takao Waho - One of the best experts on this subject based on the ideXlab platform.
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ICECS - A low-power delta-sigma modulator using dynamic-source-follower integrators
2010 17th IEEE International Conference on Electronics Circuits and Systems, 2010Co-Authors: Ryoto Yaguchi, Fumiyuki Adachi, Takao WahoAbstract:A novel low-power switched-capacitor integrator based on dynamic-source-follower Amplifiers is prOposed and applied to a 2nd-order ΔΣ modulator. Circuit simulation assuming 0.18-µm CMOS technology shows that the present integrator can drastically reduce the power dissipation compared with Conventional Op-Amp-based integrators. A figure-of-merit (FOM) of 0.172 pJ/conv·step has been predicted with a bandwidth and an SNDR of 20 kHz and 73.8dB, respectively.
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A low-power delta-sigma modulator using dynamic-source-follower integrators
2010 17th IEEE International Conference on Electronics Circuits and Systems, 2010Co-Authors: Ryoto Yaguchi, Fumiyuki Adachi, Takao WahoAbstract:A novel low-power switched-capacitor integrator based on dynamic-source-follower Amplifiers is prOposed and applied to a 2nd-order ΔΣ modulator. Circuit simulation assuming 0.18-μm CMOS technology shows that the present integrator can drastically reduce the power dissipation compared with Conventional Op-Amp-based integrators. A figure-of-merit (FOM) of 0.172 pJ/conv·step has been predicted with a bandwidth and an SNDR of 20 kHz and 73.8dB, respectively.
Ahmed M. Soliman - One of the best experts on this subject based on the ideXlab platform.
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An Intelligent Technique for GeneratingEquivalent TT Circuits Using GeneticAlgorithm
International Journal of Advanced Research in Electrical Electronics and Instrumentation Energy, 2020Co-Authors: Nariman A. Khalil, Rania F. Ahmed, Rania A. Abul Seoud, Ahmed M. SolimanAbstract:The TT filter is a basic building block in many analog signal processing applications. Genetic algorithm applications in analog design circuits play an important role with promising results. This paper introduces the TT_GA Technique. It is an intelligent technique for generating equivalent TT Circuits using genetic algorithm realization with Nullor and Pathological elements. The goal is to generate equivalent Second Generation Current Conveyor (CCII) as well as equivalent Transconductance Amplifier (TA) circuits. This Technique generates 8 different TT circuits using CCII circuits. Also, it generates 16 circuits using TA. Some of thegenerated TTcircuits and the Conventional Op-Amp realized filtersare simulated using SPICEand compared to each other’s.A standard CMOS model of 0.25 μm is used.By applying the TT_GA Technique we can get all possible solutions programmatically.
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ICECS - An intelligent technique for generating equivalent KHN circuits using genetic algorithm
2015 IEEE International Conference on Electronics Circuits and Systems (ICECS), 2015Co-Authors: Nariman A. Khalil, Rania F. Ahmed, Rania. A. Abulsoud, Ahmed M. SolimanAbstract:Genetic algorithm applications in analog design circuits play an important role with promising results. This paper introduces the GA methodology and employs KHN circuit as an application. It is an intelligent technique for generating equivalent KHN Circuits using genetic algorithm with nullor and mirror elements. The goal is to generate equivalent KHN circuits using Second Generation Current Conveyor (CCII) as well as equivalent Trans-conductance Amplifier (TA) circuits. This methodology generates 32 different KHN-CCII circuits for type A and type B. Moreover, it generates 64 KHN-TA circuits for each type. The frequency response of one of the generated KHN circuits are compared to the Conventional Op-Amp one using PSPICE and it is proved that the generated circuits have superior performance. It is worth noting that the great advantage of the prOposed GA technique is to get all realizable solutions programmatically and it is a universal technique that can be applied on any filter.
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An intelligent technique for generating equivalent KHN circuits using genetic algorithm
2015 IEEE International Conference on Electronics Circuits and Systems (ICECS), 2015Co-Authors: Nariman A. Khalil, Rania F. Ahmed, Rania. A. Abulsoud, Ahmed M. SolimanAbstract:Genetic algorithm applications in analog design circuits play an important role with promising results. This paper introduces the GA methodology and employs KHN circuit as an application. It is an intelligent technique for generating equivalent KHN Circuits using genetic algorithm with nullor and mirror elements. The goal is to generate equivalent KHN circuits using Second Generation Current Conveyor (CCII) as well as equivalent Trans-conductance Amplifier (TA) circuits. This methodology generates 32 different KHN-CCII circuits for type A and type B. Moreover, it generates 64 KHN-TA circuits for each type. The frequency response of one of the generated KHN circuits are compared to the Conventional Op-Amp one using PSPICE and it is proved that the generated circuits have superior performance. It is worth noting that the great advantage of the prOposed GA technique is to get all realizable solutions programmatically and it is a universal technique that can be applied on any filter.