The Experts below are selected from a list of 282 Experts worldwide ranked by ideXlab platform
Kees Beenakker - One of the best experts on this subject based on the ideXlab platform.
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Single-Grain Si Thin-Film Transistors for Monolithic 3D-ICs and Flexible Electronics
IEICE Transactions on Electronics, 2014Co-Authors: Ryoichi Ishihara, Kees Beenakker, Tao Chen, Jin Zhang, Miki Trifunovic, Jaber Derakhshandeh, Negin Golshani, Daniel M. R. Tajari Mofrad, Tatsuya ShimodaAbstract:We review our recent achievements in monolithic 3D-ICs and flexible electronics based on single-grain Si TFTs that are fabricated inside a single-grain with a low-temperature Process. Based on pulsed-laser crystallization and submicron sized cavities made in the substrate, amorphous-Si precursor film was converted into poly-Si having grains that are formed on predetermined positions. Using the method called µ-Czochralski Process and LPCVD a-Si precursor film, two layers of the SG Si TFT layers with the grains having a diameter of 6µm were vertically stacked with a maximum Process temperature of 550°C. Mobility for electrons and holes were 600cm2/Vs and 200cm2/Vs, respectively. As a demonstration of monolithic 3D-ICs, the two SG-TFT layers were successfully implemented into CMOS inverter, 3D 6T-SRAM and single-grain lateral PIN photo-diode with in-pixel amplifier. The SG Si TFTs were applied to flexible electronics. In this case, the a-Si precursor was prepared by doctor-blade coating of liquid-Si based on pure cyclopentasilane (CPS) on a polyimide (PI) substrate with maximum Process temperature of 350°C. The µ-Czochralski Process provided location-controlled Si grains with a diameter of 3µm and mobilities of 460 and 121cm2/Vs for electrons and holes, respectively, were obtained. The devices on PI were transferred to a plastic foil which can operate with a bending diameter of 6mm. Those results indicate that the SG TFTs are attractive for their use in both monolithic 3D-ICs and flexible electronics
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Location controlled high performance single-grain Ge TFTs on glass substrate
Solid-state Electronics, 2012Co-Authors: Tao Chen, Ryoichi Ishihara, Kees BeenakkerAbstract:Abstract We report high performance single-grain Ge TFTs by μ-Czochralski Process. Electron mobilities are 3337 cm2/Vs with on/off ratio of 108 @VDS = 0.1 V. Hole mobilities are 1719 cm2/Vs with on/off ratio of 108 @VDS = 0.05 V. The high mobility is due to improved interface property and tensile stress.
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High Performance n- and p-channel Strained Single Grain Silicon TFTs using Excimer Laser
MRS Proceedings, 2011Co-Authors: A. Baiano, Ryoichi Ishihara, Kees BeenakkerAbstract:In this paper we investigate the carriers mobility enhancement of the n- and p-channel single-grain silicon thin-film transistors (SG-TFTs) by μ-Czochralski Process at low-temperature Process (
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High performance single-grain Ge TFTs without seed substrate
2010 International Electron Devices Meeting, 2010Co-Authors: Tao Chen, M. R. Tajari Mofrad, Ryoichi Ishihara, Sten Vollebregt, Johan Van Der Cingel, M. Van Der Zwan, H. Schellevis, Kees BeenakkerAbstract:We report high performance single-grain Ge TFTs by μ-Czochralski Process. Electron mobilites are 3337cm2/Vs with on/off ratio of 108 @V DS =0.1V. Hole mobilities are 1719cm2/Vs with on/off ratio of 108 @V DS =0.05V. The high mobility is due to improved interface property and tensile stress.
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Strained Single-Grain Silicon n- and p-Channel Thin-Film Transistors by Excimer Laser
IEEE Electron Device Letters, 2010Co-Authors: A. Baiano, Ryoichi Ishihara, J. Van Der Cingel, Kees BeenakkerAbstract:We have investigated the carrier mobility enhancement of the n- and p-channel single-grain silicon thin-film transistors by the ?-Czochralski Process at a low-temperature Process (< 350°C). The high laser energy density near the ablation phenomenon that completely melts the grain filter during the crystallization is responsible for the high tensile strain of the silicon grains, which leads to carrier mobility enhancement.
Ryoichi Ishihara - One of the best experts on this subject based on the ideXlab platform.
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SPICE Modeling of Single-Grain Si TFTs using BSIMSOI
ECS Transactions, 2019Co-Authors: A. Baiano, Ryoichi Ishihara, Wim Metselaar, Nitz Saputra, John R. Long, N. Karaki, Inoue Satoshi, C.i.m. BeenakkerAbstract:Single Grain Thin-film transistors (SG-TFTs) fabricated inside a location-controlled grain by µ-Czochralski Process have as high as SOI performance. To model them, BSIMSOI with a proper modification of the mobility is proposed. The model has been verified for n- and p-channel DC and low frequency AC conditions by comparison with measurement results. Furthermore, preliminary circuit simulations are executed.
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Single Grain Si TFTs for RF and 3D ICs
ECS Transactions, 2019Co-Authors: Ryoichi Ishihara, J. Derakhshandeh, M. R. Tajari Mofrad, A. Baiano, Tao Chen, Mina Danesh, Nitz Saputra, John R. Long, C.i.m. BeenakkerAbstract:Single-grain Si TFTs have been fabricated using accurate 2D location control of large Si grain with the ?-Czochralski Process. TFTs fabricated inside the crystalline islands of 6 ?m show a mobility (600cm2/Vs) as high as that of the SOI counterpart, despite of the low-temperature (
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Single-Grain Si Thin-Film Transistors for Monolithic 3D-ICs and Flexible Electronics
IEICE Transactions on Electronics, 2014Co-Authors: Ryoichi Ishihara, Kees Beenakker, Tao Chen, Jin Zhang, Miki Trifunovic, Jaber Derakhshandeh, Negin Golshani, Daniel M. R. Tajari Mofrad, Tatsuya ShimodaAbstract:We review our recent achievements in monolithic 3D-ICs and flexible electronics based on single-grain Si TFTs that are fabricated inside a single-grain with a low-temperature Process. Based on pulsed-laser crystallization and submicron sized cavities made in the substrate, amorphous-Si precursor film was converted into poly-Si having grains that are formed on predetermined positions. Using the method called µ-Czochralski Process and LPCVD a-Si precursor film, two layers of the SG Si TFT layers with the grains having a diameter of 6µm were vertically stacked with a maximum Process temperature of 550°C. Mobility for electrons and holes were 600cm2/Vs and 200cm2/Vs, respectively. As a demonstration of monolithic 3D-ICs, the two SG-TFT layers were successfully implemented into CMOS inverter, 3D 6T-SRAM and single-grain lateral PIN photo-diode with in-pixel amplifier. The SG Si TFTs were applied to flexible electronics. In this case, the a-Si precursor was prepared by doctor-blade coating of liquid-Si based on pure cyclopentasilane (CPS) on a polyimide (PI) substrate with maximum Process temperature of 350°C. The µ-Czochralski Process provided location-controlled Si grains with a diameter of 3µm and mobilities of 460 and 121cm2/Vs for electrons and holes, respectively, were obtained. The devices on PI were transferred to a plastic foil which can operate with a bending diameter of 6mm. Those results indicate that the SG TFTs are attractive for their use in both monolithic 3D-ICs and flexible electronics
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Location controlled high performance single-grain Ge TFTs on glass substrate
Solid-state Electronics, 2012Co-Authors: Tao Chen, Ryoichi Ishihara, Kees BeenakkerAbstract:Abstract We report high performance single-grain Ge TFTs by μ-Czochralski Process. Electron mobilities are 3337 cm2/Vs with on/off ratio of 108 @VDS = 0.1 V. Hole mobilities are 1719 cm2/Vs with on/off ratio of 108 @VDS = 0.05 V. The high mobility is due to improved interface property and tensile stress.
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High Performance n- and p-channel Strained Single Grain Silicon TFTs using Excimer Laser
MRS Proceedings, 2011Co-Authors: A. Baiano, Ryoichi Ishihara, Kees BeenakkerAbstract:In this paper we investigate the carriers mobility enhancement of the n- and p-channel single-grain silicon thin-film transistors (SG-TFTs) by μ-Czochralski Process at low-temperature Process (
C.i.m. Beenakker - One of the best experts on this subject based on the ideXlab platform.
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SPICE Modeling of Single-Grain Si TFTs using BSIMSOI
ECS Transactions, 2019Co-Authors: A. Baiano, Ryoichi Ishihara, Wim Metselaar, Nitz Saputra, John R. Long, N. Karaki, Inoue Satoshi, C.i.m. BeenakkerAbstract:Single Grain Thin-film transistors (SG-TFTs) fabricated inside a location-controlled grain by µ-Czochralski Process have as high as SOI performance. To model them, BSIMSOI with a proper modification of the mobility is proposed. The model has been verified for n- and p-channel DC and low frequency AC conditions by comparison with measurement results. Furthermore, preliminary circuit simulations are executed.
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Single Grain Si TFTs for RF and 3D ICs
ECS Transactions, 2019Co-Authors: Ryoichi Ishihara, J. Derakhshandeh, M. R. Tajari Mofrad, A. Baiano, Tao Chen, Mina Danesh, Nitz Saputra, John R. Long, C.i.m. BeenakkerAbstract:Single-grain Si TFTs have been fabricated using accurate 2D location control of large Si grain with the ?-Czochralski Process. TFTs fabricated inside the crystalline islands of 6 ?m show a mobility (600cm2/Vs) as high as that of the SOI counterpart, despite of the low-temperature (
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Reliability of (100) and (110) oriented single-grain Si TFTs without seed substrate
2010 IEEE International Reliability Physics Symposium, 2010Co-Authors: Tao Chen, Ryoichi Ishihara, C.i.m. BeenakkerAbstract:We report high performance (100) and (110) oriented single-grain TFTs below 600°C by orientation controlled μ-Czochralski Process. Due to surface and in-plane orientation control, the uniformity approaches to the SOI counterpart. Electron mobilities are 732cm2/Vs for (100) and 630cm2/Vs for (110). Devices show stable performance under gate and drain stress respectively. After applying electrical stress on gate and drain for 1000s respectively, the electron mobility has not deteriorated for (100) SG-TFT and (110) SG-TFT.
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Analog and digital output lateral photodiodes fabricated by µ-Czochralski Process at low temperature
2009 Device Research Conference, 2009Co-Authors: J. Derakhshandeh, M. R. Tajari Mofrad, Ryoichi Ishihara, C.i.m. BeenakkerAbstract:We have designed and fabricated lateral photodiodes with analog and digital outputs using µ-Czochralski Process. The advantage of µ-Czochralski Process is crystallization of active silicon layer at low temperature using Excimer laser. In this Process, predefined locations on oxide with 1µm squares, called grain filters, are formed to determine the locations of single grain silicon. Then these holes are covered by 870nm PECVD TEOS oxide at 350°C to reduce the size of holes to approximately 0.1µm. After deposition of 250nm LPCVD amorphous silicon at 550°C, Excimer laser is irradiated on silicon at 400°C with 1500mJ/cm2 laser energy. This laser energy can give uniform square grains before ablation. It melts the silicon layer and then crystallization starts from bottom of grain filter where we have solid and un-melted silicon. This technique is suitable for stacking silicon layers to realize monolithic 3DIC. Fabricated TFTs inside single grains are comparable with SOI devices in term of high mobility and high frequency behavior characteristics. [1] The achieved motilities are 500cm2/VS for nMOS and 300cm2/VS for pMOS transistors. Figure 1 shows the schematics of this Process and also SEM image of crystallized silicon. The size of grains is more sensitive to laser energy and in average they are in 6µm squares.
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microstructure characterization of location controlled si islands crystallized by excimer laser in the μ Czochralski grain filter Process
Journal of Crystal Growth, 2007Co-Authors: Ryoichi Ishihara, C.i.m. Beenakker, Tatsuya Shimoda, Satoshi Inoue, J.w. Metselaar, Yasushi Hiroshima, D Danciu, F D TichelaarAbstract:Abstract Microstructure of location-controlled grains by μ-Czochralski Process was characterized with electron backscattering diffraction (EBSD) and transmission electron microscopy (TEM). We confirmed that defects in the location-controlled grain are mainly Σ 3 twin boundary generating from near the rim of the grain filter, while random grain boundaries hardly exist. Dependence of the population was investigated on Process parameters. We found that most of the Σ 3 twin boundaries have {1 1 1} facet plane, which, in same case, are massed with a nano-meter spacing. Σ 3 twin boundaries having facet planes {1 1 2} and {1 1 1}/{1 1 5} were also found to exist.
Tatsuya Shimoda - One of the best experts on this subject based on the ideXlab platform.
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Single-Grain Si Thin-Film Transistors for Monolithic 3D-ICs and Flexible Electronics
IEICE Transactions on Electronics, 2014Co-Authors: Ryoichi Ishihara, Kees Beenakker, Tao Chen, Jin Zhang, Miki Trifunovic, Jaber Derakhshandeh, Negin Golshani, Daniel M. R. Tajari Mofrad, Tatsuya ShimodaAbstract:We review our recent achievements in monolithic 3D-ICs and flexible electronics based on single-grain Si TFTs that are fabricated inside a single-grain with a low-temperature Process. Based on pulsed-laser crystallization and submicron sized cavities made in the substrate, amorphous-Si precursor film was converted into poly-Si having grains that are formed on predetermined positions. Using the method called µ-Czochralski Process and LPCVD a-Si precursor film, two layers of the SG Si TFT layers with the grains having a diameter of 6µm were vertically stacked with a maximum Process temperature of 550°C. Mobility for electrons and holes were 600cm2/Vs and 200cm2/Vs, respectively. As a demonstration of monolithic 3D-ICs, the two SG-TFT layers were successfully implemented into CMOS inverter, 3D 6T-SRAM and single-grain lateral PIN photo-diode with in-pixel amplifier. The SG Si TFTs were applied to flexible electronics. In this case, the a-Si precursor was prepared by doctor-blade coating of liquid-Si based on pure cyclopentasilane (CPS) on a polyimide (PI) substrate with maximum Process temperature of 350°C. The µ-Czochralski Process provided location-controlled Si grains with a diameter of 3µm and mobilities of 460 and 121cm2/Vs for electrons and holes, respectively, were obtained. The devices on PI were transferred to a plastic foil which can operate with a bending diameter of 6mm. Those results indicate that the SG TFTs are attractive for their use in both monolithic 3D-ICs and flexible electronics
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microstructure characterization of location controlled si islands crystallized by excimer laser in the μ Czochralski grain filter Process
Journal of Crystal Growth, 2007Co-Authors: Ryoichi Ishihara, C.i.m. Beenakker, Tatsuya Shimoda, Satoshi Inoue, J.w. Metselaar, Yasushi Hiroshima, D Danciu, F D TichelaarAbstract:Abstract Microstructure of location-controlled grains by μ-Czochralski Process was characterized with electron backscattering diffraction (EBSD) and transmission electron microscopy (TEM). We confirmed that defects in the location-controlled grain are mainly Σ 3 twin boundary generating from near the rim of the grain filter, while random grain boundaries hardly exist. Dependence of the population was investigated on Process parameters. We found that most of the Σ 3 twin boundaries have {1 1 1} facet plane, which, in same case, are massed with a nano-meter spacing. Σ 3 twin boundaries having facet planes {1 1 2} and {1 1 1}/{1 1 5} were also found to exist.
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capping layer on thin si film for µ Czochralski Process with excimer laser crystallization
Japanese Journal of Applied Physics, 2006Co-Authors: R. Vikas, Ryoichi Ishihara, Tatsuya Shimoda, Wim Metselaar, Satoshi Inoue, Yasushi Hiroshima, Daisuke Abe, Kees BeenakkerAbstract:In this paper, we report the effect of SiO2 capping layer (C/L) on the excimer laser crystallization of an amorphous Si (a-Si) thin film by the µ-Czochralski (µ-CZ) Process. With a 50-nm-thick C/L on a 50-nm-thick a-Si film, the diameter of a location-controlled grain increased to 6 µm. Single grain (SG) thin-film transistor (TFT) was fabricated with the C/L SiO2 as a part of the gate oxide. SG TFT with 50-nm-thick Si showed improved characteristics compared to that without the C/L SiO2. A field effect mobility of 340 cm2 V-1 s-1 and a subthreshold slope of 0.18 V/dec were obtained with the 50-nm-thick Si.
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Effects of Capping Layer on Grain Growth with µ-Czochralski Process during Excimer Laser Crystallization
Japanese Journal of Applied Physics, 2006Co-Authors: Ryoichi Ishihara, Tatsuya Shimoda, Wim Metselaar, Satoshi Inoue, Yasushi Hiroshima, Kees BeenakkerAbstract:The effects of a SiO2 capping layer (CL) on the excimer laser crystallization of amorphous silicon (?-Si) films are investigated during the growth of location-controlled Si grains with a ?-Czochralski (grain filter) Process by experiments and numerical simulations. The CL thinner than 400 nm for a 250-nm-thick ?-Si precursor serves as a heat reservoir and increases the average grain size to 9 ?m, while the CL thicker than 400 nm serves as a heat sink and decreases the average grain size. During laser irradiation, the CL stores heat owing to heat conduction. The CL returns a fraction of the heat into a molten pool after the laser irradiation, which results in a moderate temperature gradient of the layers beneath the molten pool. The grains grown from the molten pool increase in size owing to the long solidification duration, as a result of a slow heat extraction rate from the molten pool. While the CL thicker than 400 nm stores more heat during laser irradiation and returns only a small fraction of the heat after the laser irradiation, the grain size decreases.
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Low temperature single grain thin film transistor (LTSG-TFT) with SOI performance using cmp-flattened /spl mu/-Czochralski Process
IEEE InternationalElectron Devices Meeting 2005. IEDM Technical Digest., 2005Co-Authors: Shimada H, Hiroshima Y, Tatsuya ShimodaAbstract:We succeeded in fabricating low temperature single grain thin film transistor (LTSG-TFT) devices with excellent characteristics by using the CMP-flattened mu-Czochralski Process for 3D integrated circuits application. The LTSG-TFT devices demonstrated high drivability comparable to that of SOI-MOSFETs and an excellent gate delay time of 65psec was obtained despite the use of fully low temperature Processing
A. Baiano - One of the best experts on this subject based on the ideXlab platform.
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SPICE Modeling of Single-Grain Si TFTs using BSIMSOI
ECS Transactions, 2019Co-Authors: A. Baiano, Ryoichi Ishihara, Wim Metselaar, Nitz Saputra, John R. Long, N. Karaki, Inoue Satoshi, C.i.m. BeenakkerAbstract:Single Grain Thin-film transistors (SG-TFTs) fabricated inside a location-controlled grain by µ-Czochralski Process have as high as SOI performance. To model them, BSIMSOI with a proper modification of the mobility is proposed. The model has been verified for n- and p-channel DC and low frequency AC conditions by comparison with measurement results. Furthermore, preliminary circuit simulations are executed.
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Single Grain Si TFTs for RF and 3D ICs
ECS Transactions, 2019Co-Authors: Ryoichi Ishihara, J. Derakhshandeh, M. R. Tajari Mofrad, A. Baiano, Tao Chen, Mina Danesh, Nitz Saputra, John R. Long, C.i.m. BeenakkerAbstract:Single-grain Si TFTs have been fabricated using accurate 2D location control of large Si grain with the ?-Czochralski Process. TFTs fabricated inside the crystalline islands of 6 ?m show a mobility (600cm2/Vs) as high as that of the SOI counterpart, despite of the low-temperature (
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High Performance n- and p-channel Strained Single Grain Silicon TFTs using Excimer Laser
MRS Proceedings, 2011Co-Authors: A. Baiano, Ryoichi Ishihara, Kees BeenakkerAbstract:In this paper we investigate the carriers mobility enhancement of the n- and p-channel single-grain silicon thin-film transistors (SG-TFTs) by μ-Czochralski Process at low-temperature Process (
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Strained Single-Grain Silicon n- and p-Channel Thin-Film Transistors by Excimer Laser
IEEE Electron Device Letters, 2010Co-Authors: A. Baiano, Ryoichi Ishihara, J. Van Der Cingel, Kees BeenakkerAbstract:We have investigated the carrier mobility enhancement of the n- and p-channel single-grain silicon thin-film transistors by the ?-Czochralski Process at a low-temperature Process (< 350°C). The high laser energy density near the ablation phenomenon that completely melts the grain filter during the crystallization is responsible for the high tensile strain of the silicon grains, which leads to carrier mobility enhancement.
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Single Grain TFTs for High Speed Flexible Electronics
2009Co-Authors: A. BaianoAbstract:SG-TFTs fabricated by the ?-Czochralski Process have already reached a performance as high as that of SOI MOSFET devices. However, one of the most important and challenging goals is extending SG-TFT technology to reach a higher level of performance than that achieved with SOI technology. This thesis considers two different aspects of this question. Firstly, given the proven potential of the ?-Czochralski Process to provide high-quality crystalline silicon, it is also of interest to investigate whether the ?-Czochralski Process could also be used to produce high-mobility semiconductor materials such as germanium (Ge) sputtered at low temperature as a medium for future thin-film transistor applications, since Ge is considered to be a potential replacement for silicon (Si) because of its much higher carrier mobility. Secondly, it is also worth while investigating whether the field-effect mobilities of n- and p-channel single-grain Si TFTs could be enhanced compared with to the most advanced strained-Si on SiGe MOSFET technology by applying strain with excimer laser crystallization, despite the low Process temperature used. The study of degradation phenomena in SG-TFTs under bias stress is also of fundamental importance for the reliability analysis of such devices. A method for degradation analysis of SG-TFTs under bias stress for 2D modeling by a TCAD simulator has therefore been developed as part of the present study. Such modeling aims to improve our understanding of high voltage applications. A prototype E-Paper with active-matrix quick-response liquid powder display has been designed and developed with the aid of SG-TFT technology on this basis. The main issue in the development of such E-Paper is the requirement for a 70 V supply voltage. The necessary SG-TFT produced by the ?-Czochralski Process must therefore be designed to operate at such a high voltage, and its fabrication Process must be compatible with the ?-Czochralski Process used to make standard SG-TFTs for the development of a fully integrated E-Paper with display and driver circuits. No application using of SG-TFTs fabricated by the ?-Czochralski Process would be possible without an accurate compact SPICE model of the intended device. Many SPICE models are commercially available nowadays for both MOSFET and Poly-Si TFT technologies. However, none of those is suitable for SG-TFTs. An accurate SPICE model of SG-TFT circuits designed for digital, analog and RF applications has been developed as part of the present study. In particular, a unified SPICE model has been obtained that is applicable both to SG-TFTs fabricated by crystallization at low laser energy (which have poly-Si-like performance) and to TFTs made by crystallization at high laser energy (which have SOI-like performance).
