The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Lianggee Chen - One of the best experts on this subject based on the ideXlab platform.
-
Frame-level Data Reuse for motion-compensated temporal filtering,” in Proc
2015Co-Authors: Chingyeh Chen, Yihau Chen, Chih-chi Cheng, Lianggee ChenAbstract:Abstract Motion-compensated temporal ltering (MCTF) is an open-loop prediction scheme, so the frame-level Data Reuse for MCTF is possible. In this paper, we propose two general frame-level Data Reuse schemes which can minimize the memory bandwidth of current and reference frames, respectively. And their relationships between the required memory bandwidth and the number of searching range buffers are also formulated under the constraint of the Data dependency in Joint Scalable Video Model. Finally, we extend our analysis to pyramid MCTF and the impact of the inter-layer prediction scheme is also considered. I
-
cubic spline interpolation with overlapped window and Data Reuse for on line hilbert huang transform biomedical microprocessor
International Conference of the IEEE Engineering in Medicine and Biology Society, 2011Co-Authors: Naifu Chang, Chengyi Chiang, Tungchien Chen, Lianggee ChenAbstract:On-chip implementation of Hilbert-Huang transform (HHT) has great impact to analyze the non-linear and non-stationary biomedical signals on wearable or implantable sensors for the real-time applications. Cubic spline interpolation (CSI) consumes the most computation in HHT, and is the key component for the HHT processor. In tradition, CSI in HHT is usually performed after the collection of a large window of signals, and the long latency violates the realtime requirement of the applications. In this work, we propose to keep processing the incoming signals on-line with small and overlapped Data windows without sacrificing the interpolation accuracy. 58% multiplication and 73% division of CSI are saved after the Data Reuse between the Data windows.
-
level c Data Reuse scheme for motion estimation with corresponding coding orders
IEEE Transactions on Circuits and Systems for Video Technology, 2006Co-Authors: Chingyeh Chen, Chaotsung Huang, Yihau Chen, Lianggee ChenAbstract:The memory bandwidth reduction for motion estimation is important because of the power consumption and limited memory bandwidth in video coding systems. In this paper, we propose a Level C+ scheme which can fully Reuse the overlapped searching region in the horizontal direction and partially Reuse the overlapped searching region in the vertical direction to save more memory bandwidth compared to the Level C scheme. However, direct implementation of the Level C+ scheme may conflict with some important coding tools and then induces a lower hardware efficiency of video coding systems. Therefore, we propose n-stitched zigzag scan for the Level C+ scheme and discuss two types of 2-stitched zigzag scan for MPEG-4 and H.264 as examples. They can reduce memory bandwidth and solve the conflictions. When the specification is HDTV 720p, where the searching range is [-128,128), the required memory bandwidth is only 54%, and the increase of on-chip memory size is only 12% compared to those of traditional Level C Data Reuse scheme.
-
memory analysis of vlsi architecture for 5 3 and 1 3 motion compensated temporal filtering video coding applications
International Conference on Acoustics Speech and Signal Processing, 2005Co-Authors: Chaotsung Huang, Chingyeh Chen, Yihau Chen, Lianggee ChenAbstract:To the best of authors' knowledge, this paper presents the first work on memory analysis of VLSI architectures for motion-compensated temporal filtering (MCTF). The open-loop MCTF prediction scheme has led the revolution for hybrid video coding methods that are mainly based on the close-loop MC prediction (MCP) scheme, and it also becomes the core technology of the coming video coding standard, MPEG-21 part 13-scalable video coding (SVC). In this paper, the macroblock (MB)-level and frame-level Data Reuse schemes are analyzed for the MCTF. The MB-level Data Reuse is especially for the motion estimation (ME), and the level C+ scheme is proposed, which can further reduce the memory bandwidth of the conventional level C scheme. Frame-level Data Reuse schemes for MCTF are proposed according to the open-loop prediction nature.
-
vlsi implementation of the motion estimator with two dimensional Data Reuse
International Conference on Consumer Electronics, 1998Co-Authors: Yeongkang Lai, Yeonglin Lai, Yuanchen Liu, Lianggee ChenAbstract:This paper describes the VLSI implementation with a two-dimensional (2-D) Data-Reuse architecture for a full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two Data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently Reuse Data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
Elizabeth Yakel - One of the best experts on this subject based on the ideXlab platform.
-
visibilities and invisibilities in Data Reuse video records of practice in education
Qualitative Research, 2021Co-Authors: Elizabeth Yakel, Rebecca D Frank, Kara Suzuka, Jasmine SmithAbstract:This article investigates Data Reuse or the secondary analysis of qualitative Data, specifically video records of practice in education, which are used to study the complex cognitive, social, and l...
-
social scientists satisfaction with Data Reuse
Association for Information Science and Technology, 2016Co-Authors: Ixchel M Faniel, Adam Kriesberg, Elizabeth YakelAbstract:Much of the recent research on digital Data repositories has focused on assessing either the trustworthiness of the repository or quantifying the frequency of Data Reuse. Satisfaction with the Data Reuse experience, however, has not been widely studied. Drawing from the information systems and information science literature, we developed a model to examine the relationship between Data quality and Data Reusers' satisfaction. Based on a survey of 1,480 journal article authors who cited Inter-University Consortium for Political and Social Research ICPSR Data in published papers from 2008-2012, we found several Data quality attributes-completeness, accessibility, ease of operation, and credibility-had significant positive associations with Data Reusers' satisfaction. There was also a significant positive relationship between documentation quality and Data Reusers' satisfaction.
-
the challenges of digging Data a study of context in archaeological Data Reuse
ACM IEEE Joint Conference on Digital Libraries, 2013Co-Authors: Ixchel M Faniel, Eric Kansa, Sarah Whitcher Kansa, Julianna Barreragomez, Elizabeth YakelAbstract:Field archaeology only recently developed centralized systems for Data curation, management, and Reuse. Data documentation guidelines, standards, and ontologies have yet to see wide adoption in this discipline. Moreover, repository practices have focused on supporting Data collection, deposit, discovery, and access more than Data Reuse. In this paper we examine the needs of archaeological Data Reusers, particularly the context they need to understand, verify, and trust Data others collect during field studies. We then apply our findings to the existing work on standards development. We find that archaeologists place the most importance on Data collection procedures, but the reputation and scholarly affiliation of the archaeologists who conducted the original field studies, the wording and structure of the documentation created during field work, and the repository where the Data are housed also inform Reuse. While guidelines, standards, and ontologies address some aspects of the context Data Reusers need, they provide less guidance on others, especially those related to research design. We argue repositories need to address these missing dimensions of context to better support Data Reuse in archaeology.
-
Data Reuse and sensemaking among novice social scientists
Proceedings of the American Society for Information Science and Technology, 2012Co-Authors: Ixchel M Faniel, Adam Kriesberg, Elizabeth YakelAbstract:We know little about the Data Reuse practices of novice Data users. Yet large scale Data Reuse over the long term depends in part on uptake from early career researchers. This paper examines 22 novice social science researchers and how they make sense of social science Data. Novices are particularly interested in understanding how Data: 1) are transformed from qualitative to quantitative Data, 2) capture concepts not well-established in the literature, and 3) can be matched and merged across multiple Datasets. We discuss how novice Data users make sense of Data in these three circumstances. We find that novices seek to understand the Data producer's rationale for methodological procedures and measurement choices, which is broadly similar to researchers in other scientific communities. However we also find that they not only reflect on whether they can trust the Data producers' decisions, but also seek guidance from members of their disciplinary community. Specifically, novice social science researchers are heavily influenced by more experienced social science researchers when it comes to discovering, evaluating, and justifying their Reuse of other's Data.
Ayoung Yoon - One of the best experts on this subject based on the ideXlab platform.
-
Scientists' Data Reuse behaviors: A multilevel analysis
Journal of the Association for Information Science and Technology, 2017Co-Authors: Ayoung YoonAbstract:This study explores the factors that influence the Data Reuse behaviors of scientists and identifies the generalized patterns that occur in Data Reuse across various disciplines. This research employed an integrated theoretical framework combining institutional theory and the theory of planned behavior. The combined theoretical framework can apply the institutional theory at the individual level and extend the theory of planned behavior by including relevant contexts. This study utilized a survey method to test the proposed research model and hypotheses. Study participants were recruited from the Community of Science's (CoS) Scholar Database, and a total of 1,528 scientists responded to the survey. A multilevel analysis method was used to analyze the 1,237 qualified responses. This research showed that scientists' Data Reuse intentions are influenced by both disciplinary level factors (availability of Data repositories) and individual level factors (perceived usefulness, perceived concern, and the availability of internal resources). This study has practical implications for promoting Data Reuse practices. Three main areas that need to be improved are identified: Educating scientists, providing internal supports, and providing external resources and supports such as Data repositories.
-
social scientists Data Reuse behaviors exploring the roles of attitudinal beliefs attitudes norms and Data repositories
Library & Information Science Research, 2017Co-Authors: Ayoung Yoon, Youngseek KimAbstract:Abstract Many disciplines within the social sciences have a dynamic culture of sharing and reusing Data. Because social science Data differ from Data in the hard sciences, it is necessary to explicitly examine social science Data Reuse. This study explores the Data Reuse behaviors of social scientists in order to better understand both the factors that influence those social scientists' intentions to Reuse Data and the extent to which those factors influence actual Data Reuse. Using an integrated theoretical model developed from the theory of planned behavior (TPB) and the technology acceptance model (TAM), this study provides a broad explanation of the relationships among factors influencing social scientists' Data Reuse. A total of 292 survey responses were analyzed using structural equation modeling. Findings suggest that social scientists' Data Reuse intentions are directly influenced by the subjective norm of Data Reuse, attitudes toward Data Reuse, and perceived effort involved in Data Reuse. Attitude toward Data Reuse mediated social scientists' intentions to Reuse Data, leading to the indirect influence of the perceived usefulness and perceived concern of Data Reuse, as well as the indirect influence of the subjective norm of Data Reuse. Finally, the availability of a Data repository indirectly influenced social scientists' intentions to Reuse Data by reducing the perceived effort involved.
Peng Zhang - One of the best experts on this subject based on the ideXlab platform.
-
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level specifications. The high-throughput computation raises a high Data demand. To prevent Data accesses from being the bottleneck, on-chip memories are used as Data Reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of Data Reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of nonuniform memory partitioning. We use the stencil computation, a popular communication-intensive application domain, as a case study to show the potential benefits of nonuniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
-
an optimal microarchitecture for stencil computation acceleration based on non uniform partitioning of Data Reuse buffers
Design Automation Conference, 2014Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level (RTL) specifications. The high-throughput computation raises a high Data demand. To prevent Data accesses from being the bottleneck, on-chip memories are used as Data Reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of Data Reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of non-uniform memory partitioning. We use the stencil computation, a popular communication-intensive application domain, as a case study to show the potential benefits of non-uniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
-
polyhedral based Data Reuse optimization for configurable computing
Field Programmable Gate Arrays, 2013Co-Authors: Louisnoel Pouchet, Peng Zhang, P Sadayappan, Jason CongAbstract:Many applications, such as medical imaging, generate intensive Data traffic between the FPGA and off-chip memory. Significant improvements in the execution time can be achieved with effective utilization of on-chip (scratchpad) memories, associated with careful software-based Data Reuse and communication scheduling techniques. We present a fully automated C-to-FPGA framework to address this problem. Our framework effectively implements Data Reuse through aggressive loop transformation-based program restructuring. In addition, our proposed framework automatically implements critical optimizations for performance such as task-level parallelization, loop pipelining, and Data prefetching. We leverage the power and expressiveness of the polyhedral compilation model to develop a multi-objective optimization system for off-chip communications management. Our technique can satisfy hardware resource constraints (scratchpad size) while still aggressively exploiting Data Reuse. Our approach can also be used to reduce the on-chip buffer size subject to bandwidth constraint. We also implement a fast design space exploration technique for effective optimization of program performance using the Xilinx high-level synthesis tool.
-
An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis
2012Co-Authors: Yuxin Wang, Xu Cheng, Peng Zhang, Jason CongAbstract:Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still necessary in order to obtain better quality of results in memory system optimization. In recent years different automated memory optimization techniques have been proposed and implemented, such as Data Reuse and memory partitioning, but the problem of integrating these techniques into an applicable flow to obtain a better performance has become a challenge. In this paper we integrate Data Reuse, loop pipelining, memory partitioning, and memory merging into an automated optimization flow (AMO) for FPGA behavioral synthesis. We develop memory padding to help in the memory partitioning of indices with modulo operations. Experimental results on Xilinx Virtex-6 FPGAs show that our integrated approach can gain an average 5.8x throughput and 4.55x latency improvement compared to the approach without memory partitioning. Moreover, memory merging saves up to 44.32 % of block RAM (BRAM)
-
combined loop transformation and hierarchy allocation for Data Reuse optimization
International Conference on Computer Aided Design, 2011Co-Authors: Jason Cong, Peng Zhang, Yi ZouAbstract:External memory bandwidth is a crucial bottleneck in the majority of computation-intensive applications for both performance and power consumption. Data Reuse is an important technique for reducing the external memory access by utilizing the memory hierarchy. Loop transformation for Data locality and memory hierarchy allocation are two major steps in Data Reuse optimization flow. But they were carried out independently. This paper presents a combined approach which optimizes loop transformation and memory hierarchy allocation simultaneously to achieve global optimal results on external memory bandwidth and on-chip Data Reuse buffer size. We develop an efficient and optimal solution to the combined problem by decomposing the solution space into two subspaces with linear and nonlinear constraints respectively. We show that we can significantly prune the solution space without losing its optimality. Experimental results show that our scheme can save up to 31% of on-chip memory size compared to the separated two-step method when the memory hierarchy allocation problem is not trivial. Also, run-time complexity is acceptable for the practical cases.
Jason Cong - One of the best experts on this subject based on the ideXlab platform.
-
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level specifications. The high-throughput computation raises a high Data demand. To prevent Data accesses from being the bottleneck, on-chip memories are used as Data Reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of Data Reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of nonuniform memory partitioning. We use the stencil computation, a popular communication-intensive application domain, as a case study to show the potential benefits of nonuniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
-
an optimal microarchitecture for stencil computation acceleration based on non uniform partitioning of Data Reuse buffers
Design Automation Conference, 2014Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level (RTL) specifications. The high-throughput computation raises a high Data demand. To prevent Data accesses from being the bottleneck, on-chip memories are used as Data Reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of Data Reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of non-uniform memory partitioning. We use the stencil computation, a popular communication-intensive application domain, as a case study to show the potential benefits of non-uniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
-
polyhedral based Data Reuse optimization for configurable computing
Field Programmable Gate Arrays, 2013Co-Authors: Louisnoel Pouchet, Peng Zhang, P Sadayappan, Jason CongAbstract:Many applications, such as medical imaging, generate intensive Data traffic between the FPGA and off-chip memory. Significant improvements in the execution time can be achieved with effective utilization of on-chip (scratchpad) memories, associated with careful software-based Data Reuse and communication scheduling techniques. We present a fully automated C-to-FPGA framework to address this problem. Our framework effectively implements Data Reuse through aggressive loop transformation-based program restructuring. In addition, our proposed framework automatically implements critical optimizations for performance such as task-level parallelization, loop pipelining, and Data prefetching. We leverage the power and expressiveness of the polyhedral compilation model to develop a multi-objective optimization system for off-chip communications management. Our technique can satisfy hardware resource constraints (scratchpad size) while still aggressively exploiting Data Reuse. Our approach can also be used to reduce the on-chip buffer size subject to bandwidth constraint. We also implement a fast design space exploration technique for effective optimization of program performance using the Xilinx high-level synthesis tool.
-
An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis
2012Co-Authors: Yuxin Wang, Xu Cheng, Peng Zhang, Jason CongAbstract:Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still necessary in order to obtain better quality of results in memory system optimization. In recent years different automated memory optimization techniques have been proposed and implemented, such as Data Reuse and memory partitioning, but the problem of integrating these techniques into an applicable flow to obtain a better performance has become a challenge. In this paper we integrate Data Reuse, loop pipelining, memory partitioning, and memory merging into an automated optimization flow (AMO) for FPGA behavioral synthesis. We develop memory padding to help in the memory partitioning of indices with modulo operations. Experimental results on Xilinx Virtex-6 FPGAs show that our integrated approach can gain an average 5.8x throughput and 4.55x latency improvement compared to the approach without memory partitioning. Moreover, memory merging saves up to 44.32 % of block RAM (BRAM)
-
combined loop transformation and hierarchy allocation for Data Reuse optimization
International Conference on Computer Aided Design, 2011Co-Authors: Jason Cong, Peng Zhang, Yi ZouAbstract:External memory bandwidth is a crucial bottleneck in the majority of computation-intensive applications for both performance and power consumption. Data Reuse is an important technique for reducing the external memory access by utilizing the memory hierarchy. Loop transformation for Data locality and memory hierarchy allocation are two major steps in Data Reuse optimization flow. But they were carried out independently. This paper presents a combined approach which optimizes loop transformation and memory hierarchy allocation simultaneously to achieve global optimal results on external memory bandwidth and on-chip Data Reuse buffer size. We develop an efficient and optimal solution to the combined problem by decomposing the solution space into two subspaces with linear and nonlinear constraints respectively. We show that we can significantly prune the solution space without losing its optimality. Experimental results show that our scheme can save up to 31% of on-chip memory size compared to the separated two-step method when the memory hierarchy allocation problem is not trivial. Also, run-time complexity is acceptable for the practical cases.
