The Experts below are selected from a list of 105 Experts worldwide ranked by ideXlab platform
Mateo Valero - One of the best experts on this subject based on the ideXlab platform.
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Virtual-Physical Registers
2007Co-Authors: Antonio Gonzalez, Jose Gonzalez, Mateo Valero, Departament D&aposAbstract:A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late Stage in the pipeline, instead of doing it in the Decode Stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtualphysical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the Stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed an evaluation of the novel s..
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Virtual-Physical Registers
1998Co-Authors: Antonio Gonzalez, Jose Gonzalez, Mateo ValeroAbstract:A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late Stage in the pipeline, instead of doing it in the Decode Stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtualphysical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the Stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed an evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 21 % increase in IPC for a machine with 64 physical registers in each file) when compared with the traditional register renaming approach. 1
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HPCA - Virtual-physical registers
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture, 1Co-Authors: Antonio Gonzalez, Jose Gonzalez, Mateo ValeroAbstract:A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late Stage in the pipeline, instead of doing it in the Decode Stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the Stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed all evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 19% increase in IPC for a machine with 64 physical registers in each file) when compared with the traditional register renaming approach.
Rahul Shrestha - One of the best experts on this subject based on the ideXlab platform.
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VDAT - Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization
Communications in Computer and Information Science, 2017Co-Authors: Sumanth Gudaparthi, Rahul ShresthaAbstract:For the execution of high-end applications of present-day scenario, processor consumes profound energy and its significant fraction is due to intensive register-file access in the processor architecture. Such fraction of energy required by the processor defers to reduce with the advancement of semiconductor technology and thereby, it is essential to design energy-efficient register-file architecture for the contemporary scenario. This paper presents new register-file architecture called the bi-modal multi-banked register-file organization to capture short term reused and short lived operands to alleviate load on register file to read and write. Additionally, instruction Decode Stage of the processor architecture is restructured to capture the reused and short lived register operands. On incorporating these new features, we have conceived a processor architecture that has been synthesized and post-layout simulated in 180 nm complementary metal-oxide semiconductor (CMOS) technology node. It consumes 35 mW of total power at 200 MHz of clock frequency. The bi-modal multi-banked register-file organization stores a fraction of data bandwidth, which is local to the functional units, resulting in the reduction of cost for supplying data to the execute Stage. Subsequently, the proposed architecture is made to execute MiBench benchmark kernels and it showed up to 55% improvement in energy saving over an embedded reduced instruction-set computer (RISC) processor architecture.
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energy efficient vlsi architecture implementation of bi modal multi banked register file organization
VLSI Design and Test, 2017Co-Authors: Sumanth Gudaparthi, Rahul ShresthaAbstract:For the execution of high-end applications of present-day scenario, processor consumes profound energy and its significant fraction is due to intensive register-file access in the processor architecture. Such fraction of energy required by the processor defers to reduce with the advancement of semiconductor technology and thereby, it is essential to design energy-efficient register-file architecture for the contemporary scenario. This paper presents new register-file architecture called the bi-modal multi-banked register-file organization to capture short term reused and short lived operands to alleviate load on register file to read and write. Additionally, instruction Decode Stage of the processor architecture is restructured to capture the reused and short lived register operands. On incorporating these new features, we have conceived a processor architecture that has been synthesized and post-layout simulated in 180 nm complementary metal-oxide semiconductor (CMOS) technology node. It consumes 35 mW of total power at 200 MHz of clock frequency. The bi-modal multi-banked register-file organization stores a fraction of data bandwidth, which is local to the functional units, resulting in the reduction of cost for supplying data to the execute Stage. Subsequently, the proposed architecture is made to execute MiBench benchmark kernels and it showed up to 55% improvement in energy saving over an embedded reduced instruction-set computer (RISC) processor architecture.
Antonio Gonzalez - One of the best experts on this subject based on the ideXlab platform.
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Virtual-Physical Registers
2007Co-Authors: Antonio Gonzalez, Jose Gonzalez, Mateo Valero, Departament D&aposAbstract:A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late Stage in the pipeline, instead of doing it in the Decode Stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtualphysical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the Stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed an evaluation of the novel s..
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Virtual-Physical Registers
1998Co-Authors: Antonio Gonzalez, Jose Gonzalez, Mateo ValeroAbstract:A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late Stage in the pipeline, instead of doing it in the Decode Stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtualphysical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the Stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed an evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 21 % increase in IPC for a machine with 64 physical registers in each file) when compared with the traditional register renaming approach. 1
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International Conference on Supercomputing - Speculative execution via address prediction and data prefetching
Proceedings of the 11th international conference on Supercomputing - ICS '97, 1997Co-Authors: Jose Gonzalez, Antonio GonzalezAbstract:Data dependencies have become one of the main bottlenecks of current superscalar processors. Data speculation is gaining popularity as a mechanism to avoid the ordering imposed by data dependencies. Loads and stores are very good candidates for data speculation since their effective address has a regular behavior and then, they are highly predictable. In this paper we propose a mechanism called Address Prediction and Data Prefetching that allows load instructions to obtain their data at the Decode Stage. Besides, the effective address of load and store instructions is also predicted. These instructions and those dependent on them are speculatively executed. The technique has been evaluated for an out-of-order processor with a realistic configuration. The performance gain is about 19% in average and it is much higher for some benchmarks (up to 35%).
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HPCA - Virtual-physical registers
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture, 1Co-Authors: Antonio Gonzalez, Jose Gonzalez, Mateo ValeroAbstract:A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late Stage in the pipeline, instead of doing it in the Decode Stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the Stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed all evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 19% increase in IPC for a machine with 64 physical registers in each file) when compared with the traditional register renaming approach.
Sumanth Gudaparthi - One of the best experts on this subject based on the ideXlab platform.
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VDAT - Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization
Communications in Computer and Information Science, 2017Co-Authors: Sumanth Gudaparthi, Rahul ShresthaAbstract:For the execution of high-end applications of present-day scenario, processor consumes profound energy and its significant fraction is due to intensive register-file access in the processor architecture. Such fraction of energy required by the processor defers to reduce with the advancement of semiconductor technology and thereby, it is essential to design energy-efficient register-file architecture for the contemporary scenario. This paper presents new register-file architecture called the bi-modal multi-banked register-file organization to capture short term reused and short lived operands to alleviate load on register file to read and write. Additionally, instruction Decode Stage of the processor architecture is restructured to capture the reused and short lived register operands. On incorporating these new features, we have conceived a processor architecture that has been synthesized and post-layout simulated in 180 nm complementary metal-oxide semiconductor (CMOS) technology node. It consumes 35 mW of total power at 200 MHz of clock frequency. The bi-modal multi-banked register-file organization stores a fraction of data bandwidth, which is local to the functional units, resulting in the reduction of cost for supplying data to the execute Stage. Subsequently, the proposed architecture is made to execute MiBench benchmark kernels and it showed up to 55% improvement in energy saving over an embedded reduced instruction-set computer (RISC) processor architecture.
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energy efficient vlsi architecture implementation of bi modal multi banked register file organization
VLSI Design and Test, 2017Co-Authors: Sumanth Gudaparthi, Rahul ShresthaAbstract:For the execution of high-end applications of present-day scenario, processor consumes profound energy and its significant fraction is due to intensive register-file access in the processor architecture. Such fraction of energy required by the processor defers to reduce with the advancement of semiconductor technology and thereby, it is essential to design energy-efficient register-file architecture for the contemporary scenario. This paper presents new register-file architecture called the bi-modal multi-banked register-file organization to capture short term reused and short lived operands to alleviate load on register file to read and write. Additionally, instruction Decode Stage of the processor architecture is restructured to capture the reused and short lived register operands. On incorporating these new features, we have conceived a processor architecture that has been synthesized and post-layout simulated in 180 nm complementary metal-oxide semiconductor (CMOS) technology node. It consumes 35 mW of total power at 200 MHz of clock frequency. The bi-modal multi-banked register-file organization stores a fraction of data bandwidth, which is local to the functional units, resulting in the reduction of cost for supplying data to the execute Stage. Subsequently, the proposed architecture is made to execute MiBench benchmark kernels and it showed up to 55% improvement in energy saving over an embedded reduced instruction-set computer (RISC) processor architecture.
Stamatis Vassiliadis - One of the best experts on this subject based on the ideXlab platform.
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register renaming and dynamic speculation an alternative approach
International Symposium on Microarchitecture, 1993Co-Authors: Mayan Moudgill, Keshav Pingali, Stamatis VassiliadisAbstract:Presents a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instruction fetch Stage instead of the Decode Stage, and the mechanism is designed to operate in parallel with the tag match logic used by most cache designs. It is estimated that the critical path of the mechanism requires approximately the same number of logic levels as the tag match logic, and therefore should not impact cycle time. >
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MICRO - Register renaming and dynamic speculation: an alternative approach
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993Co-Authors: Mayan Moudgill, Keshav Pingali, Stamatis VassiliadisAbstract:Presents a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instruction fetch Stage instead of the Decode Stage, and the mechanism is designed to operate in parallel with the tag match logic used by most cache designs. It is estimated that the critical path of the mechanism requires approximately the same number of logic levels as the tag match logic, and therefore should not impact cycle time. >
