The Experts below are selected from a list of 324 Experts worldwide ranked by ideXlab platform
T.w. Williams - One of the best experts on this subject based on the ideXlab platform.
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Defect Level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996Co-Authors: J.t. De Sousa, F.m. Goncalves, J.p. Teixeira, C. Marzocca, F. Corsi, T.w. WilliamsAbstract:The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to nonequiprobable faults, which are collected from the IC layout, using the information on a typical IC process line Defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models. It is shown that DL depends on the critical areas associated with undetected faults, and their correspondent Defect densities. Simulation results are presented, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality. Moreover, results show that the efficiency of a given set of test patterns strongly depends on the physical design and Defect statistics.
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Limitations in predicting Defect Level based on stuck-at fault coverage
Proceedings of IEEE VLSI Test Symposium, 1994Co-Authors: J. Park, M. Naivar, R. Kapur, T.w. WilliamsAbstract:The stuck-at fault model has been used over decades as a guide to the test generation process and as an evaluation mechanism for the quality of the test set. As demands on quality have increased, the use of the stuck-at fault model as a predictor of the Defect Level has been questioned. This paper provides some insight on the issue and shows the limitations of using the stuck-at fault coverage to predict the Defect Level. The authors demonstrate that as Defect Level decreases the uncertainty of the estimate grows.
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VTS - Limitations in predicting Defect Level based on stuck-at fault coverage
Proceedings of IEEE VLSI Test Symposium, 1994Co-Authors: J. Park, M. Naivar, R. Kapur, M.r. Mercer, T.w. WilliamsAbstract:The stuck-at fault model has been used over decades as a guide to the test generation process and as an evaluation mechanism for the quality of the test set. As demands on quality have increased, the use of the stuck-at fault model as a predictor of the Defect Level has been questioned. This paper provides some insight on the issue and shows the limitations of using the stuck-at fault coverage to predict the Defect Level. The authors demonstrate that as Defect Level decreases the uncertainty of the estimate grows. >
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Fault modeling and Defect Level projections in digital ICs
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, 1994Co-Authors: J.t. De Sousa, F.m. Goncalves, J.p. Teixeira, T.w. WilliamsAbstract:This paper presents a new model for evaluating the Defect Level, DL, in VLSI circuits as a function of the yield, Y, and the stuck-at fault coverage, T. It is shown that the observed DL(T) curve can be accurately modeled using non equally probable, realistic faults predicted from Defect statistics data and IC layout. The deviation of DL(T) from the one estimated by the Williams-Brown equation is shown, to be caused by two effects. First, the topology of the most likely realistic faults determine their susceptibility, which is typically lower than the stuck-at fault susceptibility. Second, the incompleteness of a given test set and the detection technique (such as static voltage testing) determine a non 100% Defect coverage. The suitability of the model was assessed by means of layout fault extraction and switch-Level fault simulation, and the results obtained agree with previously published DL(T) experimental results on actual ICs.
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Defect Level as a function of fault coverage and yield
Proceedings ETC 93 Third European Test Conference, 1993Co-Authors: F. Corsi, S. Martino, T.w. WilliamsAbstract:An extension of the well known formula relating yield, fault coverage and Defect Level has been derived by removing the hypothesis of equally likely faults and exploiting the concept of critical area to evaluate the probabilities of individual faults, under the hypothesis of Poisson's yield model. A generalized weighted fault coverage figure has been introduced with reference to realistic faults and implications on the test strategy to adopt for a given product have been put into evidence.
V.d. Agrawal - One of the best experts on this subject based on the ideXlab platform.
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New graphical I/sub DDQ/ signatures reduce Defect Level and yield loss
16th International Conference on VLSI Design 2003. Proceedings., 2003Co-Authors: M.l. Bushnell, V.d. AgrawalAbstract:The measured I/sub DDQ/ current as a function of vectors is defined here as the I/sub DDQ/ signature of a chip. We examined the I/sub DDQ/ signatures of a large number of SEMATECH chips that have been classified as good or bad by a combined decision from functional, delay and scan tests. We find that a single I/sub DDQ/ threshold, whether absolute or differential, cannot separate good/bad chips with any desirable accuracy, because the good chip signature can be any one of several well-defined graphs. In general, the signature of a good chip is found to contain, discrete Levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. Based on observations, we develop a set of five graphical criteria, which provide lower Defect Level and yield loss compared to other non-I/sub DDQ/ test methods. The reason is that the graphical procedure customizes the decision for the chip-under-test, and may substantially reduce the usage of other conventional tests.
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Reducing the complexity of Defect Level modeling using the clustering effect
Proceedings Design Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), 2000Co-Authors: J.t. De Sousa, V.d. AgrawalAbstract:Accounting for the clustering effect is fundamental to increasing the accuracy of Defect Level (DL) modeling. This result has long been known in yield modeling but, as far as known, only one DL model directly accounts for it. In this paper we improve this model, reducing its number of parameters from three to two by noticing that multiple faults caused by a single Defect can also be modeled as additional clustering. Our result is supported by test data from a real production line.
Xinwei Wang - One of the best experts on this subject based on the ideXlab platform.
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the Defect Level and ideal thermal conductivity of graphene uncovered by residual thermal reffusivity at the 0 k limit
Nanoscale, 2015Co-Authors: Zaoli Xu, Shen Xu, Zhe Cheng, Nastaran Hashemi, Cheng Deng, Xinwei WangAbstract:Due to its intriguing thermal and electrical properties, graphene has been widely studied for potential applications in sensor and energy devices. However, the reported value for its thermal conductivity spans from dozens to thousands of W m−1 K−1 due to different Levels of alternations and Defects in graphene samples. In this work, the thermal diffusivity of suspended four-layered graphene foam (GF) is characterized from room temperature (RT) down to 17 K. For the first time, we identify the Defect Level in graphene by evaluating the inverse of thermal diffusivity (termed “thermal reffusivity”: Θ) at the 0 K limit. By using the Debye model of Θ = Θ0 + C × e−θ/2T and fitting the Θ–T curve to the point of T = 0 K, we identify the Defect Level (Θ0) and determine the Debye temperature of graphene. Θ0 is found to be 1878 s m−2 for the studied GF and 43–112 s m−2 for three highly crystalline graphite materials. This uncovers a 16–43-fold higher Defect Level in GF than that in pyrolytic graphite. In GF, the phonon mean free path solely induced by Defects and boundary scattering is determined as 166 nm. The Debye temperature of graphene is determined to be 1813 K, which is very close to the average theoretical Debye temperature (1911 K) of the three acoustic phonon modes in graphene. By subtracting the Defect effect, we report the ideal thermal diffusivity and conductivity (κideal) of graphene presented in the 3D foam structure in the range of 33–299 K. Detailed physics based on chemical composition and structure analysis are given to explain the κideal–T profile by comparing with those reported for suspended graphene.
Yonghang Zhang - One of the best experts on this subject based on the ideXlab platform.
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Study of Defect Levels in InAs/InAsSb Type-II Superlattice Using Pressure-Dependent Photoluminescence
2015Co-Authors: Yonghang ZhangAbstract:Abstract : We have performed pressure-dependent PL measurements on an InAs/InAs0.86 Sb0.14 T2SL structure. By fitting the measured peak energy shift and observing a quenching of the PL intensity we have determined a crossover pressure at which we believe the T2SL electron confined state reaches that of a Defect Level in the superlattice. This change in nature from a radiative to non-radiative recombination mechanism with pressure is confirmed from power dependent PL measurements. We also examined the thermal activation energies atambient pressure and close to the crossover pressure. These results support and are consistent with the determined values for the pressure coefficients of the valence and conduction band edges of the structure and the Defect Level. As a result, these experiments provide strong evidence that the Defect Level is approximately 180 meV above the conduction band edge of InAs. Consequently, these findings explain why Ga-free T2SL structures have much longer minority carrier lifetimes, a highly desirable advantage for both mid-wave and long-wave IR photodetector applications.
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evidence for a Defect Level above the conduction band edge of inas inassb type ii superlattices for applications in efficient infrared photodetectors
Applied Physics Letters, 2015Co-Authors: A D Prins, M K Lewis, Z L Bushell, S J Sweeney, Yonghang ZhangAbstract:We report pressure-dependent photoluminescence (PL) experiments under hydrostatic pressures up to 2.16 GPa on a mid-wave infrared InAs/InAs0.86Sb0.14 type-II superlattice (T2SL) structure at different pump laser excitation powers and sample temperatures. The pressure coefficient of the T2SL transition was found to be 93 ± 2 meV·GPa−1. The integrated PL intensity increases with pressure up to 1.9 GPa then quenches rapidly indicating a pressure induced Level crossing with the conduction band states at ∼2 GPa. Analysis of the PL intensity as a function of excitation power at 0, 0.42, 1.87, and 2.16 GPa shows a clear change in the dominant photo-generated carrier recombination mechanism from radiative to Defect related. From these data, evidence for a Defect Level situated at 0.18 ± 0.01 eV above the conduction band edge of InAs at ambient pressure is presented. This assumes a pressure-dependent energy shift of −11 meV·GPa−1 for the valence band edge and that the Defect Level is insensitive to pressure, both ...
Vishwani D. Agrawal - One of the best experts on this subject based on the ideXlab platform.
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DATE - Reducing the complexity of Defect Level modeling using the clustering effect
Proceedings of the conference on Design automation and test in Europe - DATE '00, 2020Co-Authors: J.t. De Sousa, Vishwani D. AgrawalAbstract:Accounting for the clustering effect is fundamental to increasing the accuracy of Defect Level (DL) modeling. This result has long been known in yield modeling but, as far as known, only one DL model directly accounts for it. In this paper we improve this model, reducing its number of parameters from three to two by noticing that multiple faults caused by a single Defect can also be modeled as additional clustering. Our result is supported by test data from a real production line.
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Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests
Journal of Electronic Testing, 2015Co-Authors: Suraj Sindia, Vishwani D. AgrawalAbstract:The objective of this work is to minimize testing cost of analog and RF circuits for which complete specification tests are available. We use an integer linear program (ILP) to eliminate as many tests as possible without exceeding the required Defect Level. The method leverages correlation among specifications, thereby avoiding the tests for specifications that are sufficiently covered by tests for other specifications. First, Monte Carlo simulation determines probabilities for each test covering all other specifications it was not originally intended for. These probabilities and the given Defect Level then define an ILP model for eliminating unnecessary tests. An hypothetical example illustration of ten specifications demonstrates that depending on the Defect Level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications followed by ILP optimization for two commercially available integrated circuits, an operational amplifier and a radio frequency power controller (RFPC), are presented as evidence of effectiveness of the technique.
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Specification test minimization for given Defect Level
2014 15th Latin American Test Workshop - LATW, 2014Co-Authors: Suraj Sindia, Vishwani D. AgrawalAbstract:An accepted industry practice for testing of analog and RF circuits is to use specification-based tests. These tests are capable of providing a very low Defect Level but tend to be long and costly. In this work, we focus on minimizing the specification-based tests without exceeding any given Defect Level. We use Monte Carlo simulation to determine the probabilities with which a test covers specifications it was not originally intended to cover. These probabilities and the given Defect Level then define an integer linear programming (ILP) model for eliminating unnecessary tests. This paper gives sufficient evidence of successful implementation of the proposed methodology. A hypothetical example of ten specifications illustrates that depending upon the Defect Level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications of a commercially available operational amplifier circuit is presented as evidence for the applicability of the technique.
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LATW - Specification test minimization for given Defect Level
2014 15th Latin American Test Workshop - LATW, 2014Co-Authors: Suraj Sindia, Vishwani D. AgrawalAbstract:An accepted industry practice for testing of analog and RF circuits is to use specification-based tests. These tests are capable of providing a very low Defect Level but tend to be long and costly. In this work, we focus on minimizing the specification-based tests without exceeding any given Defect Level. We use Monte Carlo simulation to determine the probabilities with which a test covers specifications it was not originally intended to cover. These probabilities and the given Defect Level then define an integer linear programming (ILP) model for eliminating unnecessary tests. This paper gives sufficient evidence of successful implementation of the proposed methodology. A hypothetical example of ten specifications illustrates that depending upon the Defect Level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications of a commercially available operational amplifier circuit is presented as evidence for the applicability of the technique.
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Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing
Journal of Electronic Testing, 2012Co-Authors: Suraj Sindia, Vishwani D. Agrawal, Virendra SinghAbstract:Test techniques for analog circuits characterize the input-output relationship based on coefficients of transfer function, polynomial expansion, wavelet transform, V-transform or Volterra series. However, these coefficients always suffer from errors due to measurement accuracy and noise. This paper presents closed form expressions for an upper bound on the Defect Level and a lower bound on fault coverage achievable in such analog circuit test methods. The computed bounds have been validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds on Defect Level and fault coverage in other component based test methods for linear circuits.
