The Experts below are selected from a list of 6906 Experts worldwide ranked by ideXlab platform
Michael Kraft - One of the best experts on this subject based on the ideXlab platform.
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genetic algorithm for electro mechanical co optimization of a mems accelerometer comprising a mechanical motion pre amplifier with a 2nd order sigma Delta Modulator
Symposium on Design Test Integration and Packaging of MEMS MOEMS, 2019Co-Authors: Chen Wang, Huafeng Liu, Yuan Wang, Xiaoxiao Song, Jian Bai, Michael KraftAbstract:This paper describes a novel, semi-automated methodology based on a genetic algorithm (GA) using mechanical and electronic co-optimization for micro-electromechanical systems (MEMS) devices. The use of co-optimization facilitates a MEMS design flow at system level in which mechanical and electronic domains interact to achieve better system performance. A MEMS accelerometer comprising a mechanical motion amplifier with a 2nd-order electromechanical sigma–Delta Modulator (EM-ΣΔM) interface is presented to demonstrate the effectiveness of the design approach. The strength of the approach is verified by a simulated SNR performance of 69.8 dB. Preliminary open loop measurement results match well with simulation results in which the product of sensitivity and bandwidth is improved by 100% and the sensitivity by 141% compared to a device designed in a conventional way.
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low noise vacuum mems closed loop accelerometer using sixth order multi feedback loops and local resonator sigma Delta Modulator
International Conference on Micro Electro Mechanical Systems, 2014Co-Authors: Fang Chen, Weizheng Yuan, Honglong Chang, Ioannis Zeimpekis, Michael KraftAbstract:This paper reports on the design, implementation of a novel sixth-order sigma-Delta Modulator (ΣΔM) MEMS closed-loop accelerometer with extended bandwidth in a vacuum environment (~0.5Torr), which can coexist on a single die (or package) with other sensors requiring vacuum packaging. The fully differential accelerometer sensing element with a large proof mass (4×7mm2) was designed and fabricated on a Silicon-on-Insulator (SOI) wafer with 50μm-thick structural layer. Four electronic integrators were cascaded with the sensing element for high-order noise shaping ability. The local feedback paths created a local resonator producing a notch to further suppress the total in-band quantization noise. Measurement results show the overall noise floor achieved was -120dBg/√Hz, which is equivalent to a noise acceleration value of 1.2μg/√Hz in a 500Hz bandwidth; the scale factor was 950mV/g for input accelerations up to ±6g.
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mems gyroscope control system using a band pass continuous time sigma Delta Modulator
Science in China Series F: Information Sciences, 2013Co-Authors: Zhenchuan Yang, Zhanfei Wang, Haitao Ding, Michael KraftAbstract:This paper presents a MEMS gyroscope control system of using a high-order band-pass continuous-time sigma-Delta Modulator. Compared with a low-pass discrete-time sigma-Delta Modulator based solution, the band-pass Modulator can considerably decrease the sampling frequency; moreover, the continuous-time architecture has an obvious advantage on PCB prototyping and shorter lead time of the implementation in hardware. System level simulations using MATLAB/Simulink show the proposed sixth order sigma-Delta Modulator can achieve a high SNR of 100 dB for an angular rate input with an amplitude of 200°/s and a frequency of 32 Hz. A PCB circuit implementation is simulated using Orcad/PSpice to analyze the stability, and implemented in hardware. Measurement of the power spectral density of the output bitstream reveals a noise floor of −90 dBV/Hz1/2. The prototype is tested on a rate table with an angular rate input, verifying that the principle of the approach of using an electro-mechanical band-pass sigma-Delta Modulator control system for a MEMS gyroscope.
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multi stage noise shaping sigma Delta Modulator mash for capacitive mems accelerometers
Sensors and Actuators A-physical, 2012Co-Authors: Bader Almutairi, Michael KraftAbstract:Abstract Electromechanical multi stage noise shaping (MASH) sigma–Delta Modulator (ΣΔM) has the advantages of inherent stability, high dynamic range, and high overload input level compared with the single loop sigma–Delta-Modulator approach. In this paper, a fourth order electromechanical MASH is studied by Simulink modelling and hardware implementation using surface mount PCB technology. The accelerometer used in the study is fabricated using a Silicon on Insulator (SOI) wafer with a device layer thickness of 50 μm, using a dicing free and dry release process. The experimental results confirm the concept of the MASH structure and show its potential as a closed loop interface concept for a high performance capacitive MEMS accelerometer. The 4th order MASH electromechanical ΣΔM system improves the performance of the 2nd order electromechanical ΣΔM by 20 dB, and shows a noise floor of −110 dB. Furthermore, the system is capable of handling an acceleration input of up to ±1.5 g. However, the MASH-ΣΔM is sensitive to the sensor and system parameters variation; it exhibited performance degradation of 10 dB, due to a leakage of the quantization noise to the input signal.
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multi stage noise shaping sigma Delta Modulator mash for capacitive mems accelerometers
Procedia Engineering, 2011Co-Authors: Bader Almutairi, Michael KraftAbstract:Abstract Electromechanical multi stage noise shaping sigma-Delta Modulator (MASH) has the advantages of inherent stability, high dynamic range, and high overload input level compared with the single loop sigma-Delta-Modulator approach. In this paper, a fourth order electromechanical MASH is studied by Simulink modeling and hardware implementation using surface mount PCB technology. The accelerometer used in the study is fabricated using a Silicon on Insulator (SOI) wafer with a device layer thickness of 50um, using a dicing free and dry release process. The experimental results confirm the concept of the MASH structure and show its potential as a closed loop interface concept for a high performance capacitive MEMS accelerometer.
A Rodriguezvazquez - One of the best experts on this subject based on the ideXlab platform.
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a cmos 110 db 40 ks s programmable gain chopper stabilized third order 2 1 cascade sigma Delta Modulator for low power high linearity automotive sensor asics
IEEE Journal of Solid-state Circuits, 2005Co-Authors: J. M. De La Rosa, Sara Escalera, Fernando Medeiro, B Perezverdu, O. Guerra, A RodriguezvazquezAbstract:This paper describes a 0.35-/spl mu/m CMOS chopper-stabilized switched-capacitor 2-1 cascade /spl Sigma//spl Delta/ Modulator for automotive sensor interfaces. The Modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (/spl times/0.5,/spl times/1,/spl times/2, and /spl times/4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40/spl deg/C to 175/spl deg/C). In order to relax the amplifier's dynamic requirements for the different Modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the Modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm/sup 2/ silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution /spl Sigma//spl Delta/ Modulators.
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a cmos 0 8 spl mu m transistor only 1 63 mhz switched current bandpass spl sigma spl Delta Modulator for am signal a d conversion
IEEE Journal of Solid-state Circuits, 2000Co-Authors: J. M. De La Rosa, B Perezverdu, R Del Rio, A RodriguezvazquezAbstract:This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ Modulator (BP-/spl Sigma//spl Delta/M) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This Modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z/sup -1//spl rarr/-z/sup -2/) to a 1-bit second-order low-pass /spl Sigma//spl Delta/ Modulator (LP-/spl Sigma//spl Delta/M). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the Modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz.
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top down design of high performance sigma Delta Modulators
1998Co-Authors: Fernando Medeiro, Angel Perezverdu, A RodriguezvazquezAbstract:1. Introduction. 2. Oversampling Sigma-Delta A/D Converters: Basic Concepts and State of the Art. 3. Modeling of Error Mechanisms in Sigma-Delta Modulators. 4. Behavioral Simulation of Sigma-Delta Modulators. 5. SDOPT+FRIDGE: Tools for the Automatic Design of Sigma-Delta Modulators. 6. Integrated Circuit Design (I): A 17-bit 40k Sample/s Fourth-Order Cascade Sigma-Delta Modulator. 7. Integrated Circuit Design (II): A 13-bit 2.2MSample/s Fourth-Order Cascade Multi-Bit Sigma-Delta Modulator. References. Appendix. Index.
J. M. De La Rosa - One of the best experts on this subject based on the ideXlab platform.
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a cmos 110 db 40 ks s programmable gain chopper stabilized third order 2 1 cascade sigma Delta Modulator for low power high linearity automotive sensor asics
IEEE Journal of Solid-state Circuits, 2005Co-Authors: J. M. De La Rosa, Sara Escalera, Fernando Medeiro, B Perezverdu, O. Guerra, A RodriguezvazquezAbstract:This paper describes a 0.35-/spl mu/m CMOS chopper-stabilized switched-capacitor 2-1 cascade /spl Sigma//spl Delta/ Modulator for automotive sensor interfaces. The Modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (/spl times/0.5,/spl times/1,/spl times/2, and /spl times/4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40/spl deg/C to 175/spl deg/C). In order to relax the amplifier's dynamic requirements for the different Modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the Modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm/sup 2/ silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution /spl Sigma//spl Delta/ Modulators.
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a cmos 0 8 spl mu m transistor only 1 63 mhz switched current bandpass spl sigma spl Delta Modulator for am signal a d conversion
IEEE Journal of Solid-state Circuits, 2000Co-Authors: J. M. De La Rosa, B Perezverdu, R Del Rio, A RodriguezvazquezAbstract:This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ Modulator (BP-/spl Sigma//spl Delta/M) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This Modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z/sup -1//spl rarr/-z/sup -2/) to a 1-bit second-order low-pass /spl Sigma//spl Delta/ Modulator (LP-/spl Sigma//spl Delta/M). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the Modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz.
E Sanchezsinencio - One of the best experts on this subject based on the ideXlab platform.
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a continuous time sigma Delta Modulator with 88 db dynamic range and 1 1 mhz signal bandwidth
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Shouli Yan, E SanchezsinencioAbstract:This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ Modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ Modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ Modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the Modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.
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a continuous time spl sigma spl Delta Modulator with 88db dynamic range and 1 1mhz signal bandwidth
International Solid-State Circuits Conference, 2003Co-Authors: Shouli Yan, E SanchezsinencioAbstract:A baseband continuous-time multi-bit /spl Sigma//spl Delta/ Modulator achieves 88dB dynamic range over a 1.1MHz signal bandwidth consuming 62mW from a 3.3V supply. Excess loop delay encountered in conventional continuous-time Modulators is eliminated by the proposed architecture. Clock-jitter sensitivity is considerably reduced compared with prior designs.
B Perezverdu - One of the best experts on this subject based on the ideXlab platform.
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a cmos 110 db 40 ks s programmable gain chopper stabilized third order 2 1 cascade sigma Delta Modulator for low power high linearity automotive sensor asics
IEEE Journal of Solid-state Circuits, 2005Co-Authors: J. M. De La Rosa, Sara Escalera, Fernando Medeiro, B Perezverdu, O. Guerra, A RodriguezvazquezAbstract:This paper describes a 0.35-/spl mu/m CMOS chopper-stabilized switched-capacitor 2-1 cascade /spl Sigma//spl Delta/ Modulator for automotive sensor interfaces. The Modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (/spl times/0.5,/spl times/1,/spl times/2, and /spl times/4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40/spl deg/C to 175/spl deg/C). In order to relax the amplifier's dynamic requirements for the different Modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the Modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm/sup 2/ silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution /spl Sigma//spl Delta/ Modulators.
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a cmos 0 8 spl mu m transistor only 1 63 mhz switched current bandpass spl sigma spl Delta Modulator for am signal a d conversion
IEEE Journal of Solid-state Circuits, 2000Co-Authors: J. M. De La Rosa, B Perezverdu, R Del Rio, A RodriguezvazquezAbstract:This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ Modulator (BP-/spl Sigma//spl Delta/M) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This Modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z/sup -1//spl rarr/-z/sup -2/) to a 1-bit second-order low-pass /spl Sigma//spl Delta/ Modulator (LP-/spl Sigma//spl Delta/M). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the Modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz.