The Experts below are selected from a list of 1560 Experts worldwide ranked by ideXlab platform
M. Fujita - One of the best experts on this subject based on the ideXlab platform.
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Simulation-Based Verification Techniques for System-Level Designs
Verification Techniques for System-Level Design, 2020Co-Authors: M. Fujita, I. Ghosh, Mukul R. PrasadAbstract:This chapter discusses the various aspects of simulation-based verification for high-level hardware Designs. Simulation-based verification is currently the most widely used verification technique in the industry. With increasing Design sizes, writing the simulation test-bench and ensuring the quality of those tests in verifying the complete Design will be a huge challenge in the multibillion-transistor Designs of the future. The different types of simulations possible at various levels of Design Abstraction are examined. In the simulation method, a set of simulation models is used in some electronic Design automation (EDA) tool that exercises the implementation with a series of input simulation patterns. The output of the simulation is captured and examined for conformity with the output of the specification. The various core algorithms used in commercial simulation tools are elaborated and the various drawbacks and pitfalls of simulation-based verification are highlighted. Some techniques to address each of those drawbacks are discussed in detail. Various automation techniques and tools that are being used to make the tedious task of test-bench generation easier are also discussed. These techniques, coupled with model-driven test generation and higher levels of Design Abstraction, can be used to make this verification technique scale to multibillion-transistor Designs of the future. The chapter concludes with an industrial case study that used simulation-based verification for verifying the Design of a 10 GB Ethernet switch chip.
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VLSI Design - High level Design validation: current practices and future directions
17th International Conference on VLSI Design. Proceedings., 2004Co-Authors: I. Ghosh, R. Mukherjee, Mukul R. Prasad, M. FujitaAbstract:This paper describes about the increasing complexity of VLSI Design, time to market pressures. The two major paradigms to address the difficulties currently being faced by industry are: (1) the use of higher levels of Design Abstraction and (2) efficient and seamless Design reuse. Current industrial practices and academic research in Design verification and validation are also discussed.
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High level Design validation: current practices and future directions
17th International Conference on VLSI Design. Proceedings., 2004Co-Authors: I. Ghosh, M. Prasad, R. Mukherjee, M. FujitaAbstract:This paper describes about the increasing complexity of VLSI Design, time to market pressures. The two major paradigms to address the difficulties currently being faced by industry are: (1) the use of higher levels of Design Abstraction and (2) efficient and seamless Design reuse. Current industrial practices and academic research in Design verification and validation are also discussed.
D.d. Gajski - One of the best experts on this subject based on the ideXlab platform.
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Structural operational semantics for supporting multi-cycle operations in RTL HDLs
Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design 2005. MEMOCODE '05., 2005Co-Authors: Shuqing Zhao, D.d. GajskiAbstract:In this paper we formally define an operational semantics framework RTL++ for modeling behavioral RTL hardware IP. The semantics we define is neutral to existing HDLs and extends traditional sense RTL by natively supporting pipelined and multi-cycled operations with a unified register variable type. We believe this formalization help to guide the Design of new HDLs or extensions of existing HDLs in terms of elevating RTL Design Abstraction level and also bridging the current HDL semantic gap among synthesis, simulation and formal verification tools. The intra-module and inter-module execution of RTL++ semantics are specified in Plotkin-style structural operational semantics framework. An example of implementing the RTL++ extension of SystemC is presented along with experimental results showing the benefit of modeling in RTL++.
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Defining an enhanced RTL semantics
Design Automation and Test in Europe, 2005Co-Authors: Shuqing Zhao, D.d. GajskiAbstract:In this paper, we formally define an enhanced RTL semantics. This is intended to elevate the RTL Design Abstraction level and help bridge the HDL semantic gap among synthesis, simulation and formal verification tools. We define the enhanced semantics based on a new RTL++ language that supports pipelined operations using a new pipelined register variable concept. The execution semantics of RTL++ is specified in a structural operational semantics style aimed at forming the basis for related simulation and formal verification algorithm development. An RFSM model is defined to support natively the synthesis semantics of RTL++. We also present an example of extending SystemC to support the notion of a pipelined register variable.
Xuanyao Fong - One of the best experts on this subject based on the ideXlab platform.
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device circuit architecture co Design of reliable stt mram
Design Automation and Test in Europe, 2015Co-Authors: Zoha Pajouhi, Xuanyao FongAbstract:Spin transfer torque magnetic random access memory (STT-MRAM), using magnetic tunnel junctions (MTJ) has garnered significant attention in the research community due to its immense potential for on-chip, high-density and non-volatile memory. However, process variations may significantly impact the achievable yield in STT-MRAM. To this end, several yield enhancement techniques that improve STT-MRAM failures at the bit-cell, and at the architecture level of Design Abstraction have been proposed in the literature. However, these techniques may lead to a suboptimal Design because they do not consider the impact of Design choices at every level of Design Abstraction. In this paper, we propose a unified device-circuit-architecture co-Design framework to optimize and enhance the yield of STT-MRAM. We studied the interaction between device parameters (viz. energy barrier height) and bit-cell level parameters (viz. transistor width), together with different Error Correcting Codes (ECC) to optimize the robustness and energy efficiency of STT-MRAM cache. The advantages of our proposed approach to STT-MRAM Design are explored at the 32nm technology node. We show that for a target yield of 500 Defects Per Million (DPM) for an example array with 64-bit word length, our proposed approach with realistic parameters can save up to 15% and 13% in cell area and total power consumption, respectively, in comparison with a Design that does not use any array level yield enhancement technique.
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DATE - Device/circuit/architecture co-Design of reliable STT-MRAM
Design Automation & Test in Europe Conference & Exhibition (DATE) 2015, 2015Co-Authors: Zoha Pajouhi, Xuanyao FongAbstract:Spin transfer torque magnetic random access memory (STT-MRAM), using magnetic tunnel junctions (MTJ) has garnered significant attention in the research community due to its immense potential for on-chip, high-density and non-volatile memory. However, process variations may significantly impact the achievable yield in STT-MRAM. To this end, several yield enhancement techniques that improve STT-MRAM failures at the bit-cell, and at the architecture level of Design Abstraction have been proposed in the literature. However, these techniques may lead to a suboptimal Design because they do not consider the impact of Design choices at every level of Design Abstraction. In this paper, we propose a unified device-circuit-architecture co-Design framework to optimize and enhance the yield of STT-MRAM. We studied the interaction between device parameters (viz. energy barrier height) and bit-cell level parameters (viz. transistor width), together with different Error Correcting Codes (ECC) to optimize the robustness and energy efficiency of STT-MRAM cache. The advantages of our proposed approach to STT-MRAM Design are explored at the 32nm technology node. We show that for a target yield of 500 Defects Per Million (DPM) for an example array with 64-bit word length, our proposed approach with realistic parameters can save up to 15% and 13% in cell area and total power consumption, respectively, in comparison with a Design that does not use any array level yield enhancement technique.
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Spin-transfer torque MRAMs for low power memories: Perspective and prospective
IEEE Sensors Journal, 2012Co-Authors: Charles Augustine, Niladri Narayan Mojumder, Xuanyao Fong, Sri Harsha Choday, Sang Phill Park, Kaushik RoyAbstract:Electron-spin based data storage for on-chip memories has the potential for ultra-high density, low-power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device and bit-cell level Design techniques. Such Design methods at various levels of Design Abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.
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STT-MRAMs for future universal memories: Perspective and prospective
2012 28th International Conference on Microelectronics - Proceedings MIEL 2012, 2012Co-Authors: Charles Augustine, Niladri Narayan Mojumder, Xuanyao Fong, Harsha Choday, Sang Phill Park, Kaushik RoyAbstract:Electron-spin based data storage for on-chip memories has the potential for ultra-high density, low-power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device and bit-cell level Design techniques. Such Design methods at various levels of Design Abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications. View full abstract
I. Ghosh - One of the best experts on this subject based on the ideXlab platform.
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Simulation-Based Verification Techniques for System-Level Designs
Verification Techniques for System-Level Design, 2020Co-Authors: M. Fujita, I. Ghosh, Mukul R. PrasadAbstract:This chapter discusses the various aspects of simulation-based verification for high-level hardware Designs. Simulation-based verification is currently the most widely used verification technique in the industry. With increasing Design sizes, writing the simulation test-bench and ensuring the quality of those tests in verifying the complete Design will be a huge challenge in the multibillion-transistor Designs of the future. The different types of simulations possible at various levels of Design Abstraction are examined. In the simulation method, a set of simulation models is used in some electronic Design automation (EDA) tool that exercises the implementation with a series of input simulation patterns. The output of the simulation is captured and examined for conformity with the output of the specification. The various core algorithms used in commercial simulation tools are elaborated and the various drawbacks and pitfalls of simulation-based verification are highlighted. Some techniques to address each of those drawbacks are discussed in detail. Various automation techniques and tools that are being used to make the tedious task of test-bench generation easier are also discussed. These techniques, coupled with model-driven test generation and higher levels of Design Abstraction, can be used to make this verification technique scale to multibillion-transistor Designs of the future. The chapter concludes with an industrial case study that used simulation-based verification for verifying the Design of a 10 GB Ethernet switch chip.
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VLSI Design - High level Design validation: current practices and future directions
17th International Conference on VLSI Design. Proceedings., 2004Co-Authors: I. Ghosh, R. Mukherjee, Mukul R. Prasad, M. FujitaAbstract:This paper describes about the increasing complexity of VLSI Design, time to market pressures. The two major paradigms to address the difficulties currently being faced by industry are: (1) the use of higher levels of Design Abstraction and (2) efficient and seamless Design reuse. Current industrial practices and academic research in Design verification and validation are also discussed.
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High level Design validation: current practices and future directions
17th International Conference on VLSI Design. Proceedings., 2004Co-Authors: I. Ghosh, M. Prasad, R. Mukherjee, M. FujitaAbstract:This paper describes about the increasing complexity of VLSI Design, time to market pressures. The two major paradigms to address the difficulties currently being faced by industry are: (1) the use of higher levels of Design Abstraction and (2) efficient and seamless Design reuse. Current industrial practices and academic research in Design verification and validation are also discussed.
Santonu Sarkar - One of the best experts on this subject based on the ideXlab platform.
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ISEC - ThrustHetero: A Framework to Simplify Heterogeneous Computing Platform Programming using Design Abstraction
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference) - ISEC'19, 2019Co-Authors: Ajai V. George, Sankar Manoj, Santonu SarkarAbstract:Heterogeneous compute architectures like Multi-Core CPUs, CUDA GPUs, and Intel Xeon Phis have become prevalent over the years. While heterogeneity makes architecture specific features available to the programmer, it also makes application development difficult, as one needs to plan for optimal usage of architectural features, suitable partitioning of the workload, communication and data transfer among the participating devices. A suitable Design Abstraction that hides such variabilities of the underlying devices and at the same time exploits their computing capabilities, can improve developer productivity. In this work, we present "ThrustHetero", a lightweight framework based on NVIDIA's Thrust, that provides an Abstraction over several devices such as GPUs, Xeon Phis and multicore, yet allows developers to easily leverage the full compute capability of these devices. We also demonstrate a novel method for workload distribution in two stages - micro-benchmarking during framework installations to find good proportions and then using this information during application execution. We consider four classes of applications based on how they would perform on various computing architectures on the basis of the amount of branching present in the application. We show that the framework produces a good workload distribution proportions for each class of application and also show that the framework is scalable and portable. Further, we compare the performance and ease of development when using the framework with the native versions of various benchmarks and obtain favorable results.
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HiPC - Thrust++: Extending Thrust Framework for Better Abstraction and Performance
2017 IEEE 24th International Conference on High Performance Computing (HiPC), 2017Co-Authors: Ajai V. George, Sankar Manoj, Sanket Rajan Gupte, Sayantan Mitra, Santonu SarkarAbstract:A good Design Abstraction framework for high performance computing should provide a higher level programming Abstraction that strikes a balance between the Abstraction and visibility over the hardware so that the software developer can write a portable software without having to understand the hardware nuances, yet exploit the compute power optimally. In this paper we have analyzed a popular Design Abstraction framework called "Thrust" from NVIDIA, and proposed an extension called Thrust++ that provides Abstraction over the memory hierarchy of an NVIDIA GPU. Thrust++ allows developers to make efficient use of shared memory and overall, provides better control over the GPU memory hierarchy while writing applications in Thrust style for the CUDA backend. We have shown that when applications are written for the CUDA backend using Thrust++, they have minimal performance degradation when compared to their equivalent CUDA versions. Further, Thrust++ provides almost 4x speedup when compared to Thrust, for certain compute intensive kernels that repeatedly use the reduce operation.
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ICPP Workshops - An Empirical Evaluation of Design Abstraction and Performance of Thrust Framework
2017 46th International Conference on Parallel Processing Workshops (ICPPW), 2017Co-Authors: Ajai V. George, Sankar Manoj, Sanket Rajan Gupte, Santonu SarkarAbstract:High performance computing applications are far more difficult to write, therefore, practitioners expect a well-tuned software to last long and provide optimized performance even when the hardware is upgraded. It may also be necessary to write software using sufficient Abstraction over the hardware so that it is capable of running on heterogeneous architecture. Therefore, it is required to have a proper programming Abstraction paradigm that strikes a balance between the Abstraction and visibility over the hardware so that the programmer can write a program without having to understand the hardware nuances, yet exploit the compute power optimally. In this paper we have analyzed the power of Design Abstraction and performance of a popular Design Abstraction framework called Thrust. We have shown quantitatively that while it is easier to write an application using Thrust compared to writing the same in the native CUDA or OpenMP backends, the framework does not provide any Abstraction over the memory hierarchy of the underlying backend to the programmer. We have compared the performance of three Thrust applications with their corresponding native versions in CUDA, OpenMP, Xeon-Phi and the CPP backends and demonstrate that the current Thrust version performs poorly in most of the cases when the application is compute intensive. However, the framework provides close to the native performance for a non-compute intensive applications. We analyze the reasons for the performance and highlight the improvements necessary for the framework.
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SEM4HPC@HPDC - How Effective is Design Abstraction in Thrust?: An Empirical Evaluation
Proceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications - SEM4HPC '17, 2017Co-Authors: Ajai V. George, Sankar Manoj, Sanket Rajan Gupte, Santonu SarkarAbstract:High performance computing applications are far more difficult to write, therefore, practitioners expect a well-tuned software to last long and provide optimized performance even when the hardware is upgraded. It may also be necessary to write software using sufficient Abstraction over the hardware so that it is capable of running on heterogeneous architecture. A good Design Abstraction paradigm strikes a balance between the Abstraction and visibility over the hardware. This allows the programmer to write applications without having to understand the hardware nuances while exploiting the computing power optimally. In this paper we have analyzed the power of Design Abstraction of a popular Design Abstraction framework called Thrust both from ease of programming and performance perspectives. We have shown that while Thrust framework is good in describing an algorithm compared to the native CUDA or OpenMP version but it has quite a few Design limitations. With respect to CUDA it does not provide any Abstraction over the shared, texture or constant memory usage to the programmer. We have compared the performance of a Thrust application code in CUDA, OpenMP and the CPP backends with respect to the native versions (implementing exactly same algorithm), written for these backends and found that the current Thrust version performs poorly in most of the cases. While we conclude that the framework is not ready for writing applications that can exploit the optimal performance from the hardware, we also highlight the improvements necessary for the framework to make the performance comparable.
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An Empirical Evaluation of Design Abstraction and Performance of Thrust Framework
2017 46th International Conference on Parallel Processing Workshops (ICPPW), 2017Co-Authors: Ajai V. George, Sankar Manoj, Sanket Rajan Gupte, Santonu SarkarAbstract:High performance computing applications are far more difficult to write, therefore, practitioners expect a well-tuned software to last long and provide optimized performance even when the hardware is upgraded. It may also be necessary to write software using sufficient Abstraction over the hardware so that it is capable of running on heterogeneous architecture. Therefore, it is required to have a proper programming Abstraction paradigm that strikes a balance between the Abstraction and visibility over the hardware so that the programmer can write a program without having to understand the hardware nuances, yet exploit the compute power optimally. In this paper we have analyzed the power of Design Abstraction and performance of a popular Design Abstraction framework called Thrust. We have shown quantitatively that while it is easier to write an application using Thrust compared to writing the same in the native CUDA or OpenMP backends, the framework does not provide any Abstraction over the memory hierarchy of the underlying backend to the programmer. We have compared the performance of three Thrust applications with their corresponding native versions in CUDA, OpenMP, Xeon-Phi and the CPP backends and demonstrate that the current Thrust version performs poorly in most of the cases when the application is compute intensive. However, the framework provides close to the native performance for a non-compute intensive applications. We analyze the reasons for the performance and highlight the improvements necessary for the framework.
