The Experts below are selected from a list of 312 Experts worldwide ranked by ideXlab platform

Jerzy Kanicki - One of the best experts on this subject based on the ideXlab platform.

  • p 11 electrical properties and stability of dual gate coplanar homojunction amorphous indium gallium zinc oxide thin film transistor
    Unknown Journal, 2011
    Co-Authors: Gwanghyeo Aek, Jerzy Kanicki, Ale Kuo, Katsumi Abe, Hideya Kumomi
    Abstract:

    electrical characteristics and stabilities of dual-gate (DG) coplanar homojunction amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) are described. When the gate Voltage is applied on top and bottom electrodes, the DG a-IGZO TFT showed an excellent electrical performance with the sub- Threshold swing of 99 mV/dec, the mobility of 15.1 cm 2 /V·s and the on-off ratio of 10 9 . Under positive bias temperature stress, the Device Threshold Voltage shifts about +4.5V after 10,000 seconds, while its shifts under negative bias temperature stress are very small. The effect of TFT illumination is also discussed.

  • p 11 electrical properties and stability of dual gate coplanar homojunction amorphous indium gallium zinc oxide thin film transistor
    49th Annual SID Symposium Seminar and Exhibition 2011 Display Week 2011, 2011
    Co-Authors: Gwanghyeo Aek, Jerzy Kanicki, Ale Kuo, Katsumi Abe, Hideya Kumomi
    Abstract:

    The electrical characteristics and stabilities of dual-gate (DG) coplanar homojunction amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) are described. When the gate Voltage is applied on top and bottom electrodes, the DG a-IGZO TFT showed an excellent electrical performance with the sub-Threshold swing of 99 mV/dec, the mobility of 15.1 cm2/V·s and the on-off ratio of 109. Under positive bias temperature stress, the Device Threshold Voltage shifts about +4.5V after 10,000 seconds, while its shifts under negative bias temperature stress are very small. The effect of TFT illumination is also discussed.

  • Advanced Amorphous Silicon Thin-Film Transistors for AM-OLEDs: Electrical Performance and Stability
    IEEE Transactions on Electron Devices, 2008
    Co-Authors: Alex Kuo, Tae Kyung Won, Jerzy Kanicki
    Abstract:

    We fabricated and characterized the advanced amorphous silicon thin-film transistors with a bilayer structure for both the active and gate dielectric films. The electrical field across the gate insulator has a significant influence on the Device Threshold Voltage electrical stability. We show that high thin-film transistor stability can be achieved even under the presence of a high channel current. Its electrical and high-temperature stability improves up to a factor of five when the TFT biasing condition changes from the linear to the saturation region of operation.

T.-y. Chan - One of the best experts on this subject based on the ideXlab platform.

  • Threshold Voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers
    IEEE Transactions on Electron Devices, 1992
    Co-Authors: J.f. Chen, R. Solomon, T.-y. Chan
    Abstract:

    C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate Voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of +or-150 AA was found. This thickness variation causes as much as a 100-mV variation in the Device Threshold Voltage. The silicon-film thickness variation and Threshold-Voltage variation across a wafer shows a linear correlation dependence for a fully depleted Device. C-V measurements of the back-gate Device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed. >

Dragica Vasileska - One of the best experts on this subject based on the ideXlab platform.

  • Static Analysis of Random Telegraph Noise in a 45-nm Channel Length Conventional MOSFET Device: Threshold Voltage and ON-Current Fluctuations
    IEEE Transactions on Nanotechnology, 2011
    Co-Authors: Nabil Ashraf, Dragica Vasileska
    Abstract:

    In this paper, we investigate the Threshold Voltage and ON-current fluctuations due to the presence of charged traps located in the middle portion of the channel when the trap is moved from the source end to the drain end of the channel in a 45-nm technology node Device with an effective channel length of 35 nm. Our thorough investigations suggest that the Threshold Voltage fluctuation and its standard deviation are much larger than the ON-current fluctuation since in the ON-state screening effectively reduces the strength of the trap Coulomb potential, which is not the case in the OFF-state. We believe that this is a first study that simultaneously investigates the effects of random dopant and random telegraph noise fluctuations that utilizes particle-based Device simulators that correctly account for the long-range and the short-range Coulomb interaction. Unique feature of the approach is the proper incorporation, in a self-consistent manner, of the short-range Coulomb interaction via the real-space molecular dynamics routine. Indeed, Vasileska has pioneered this technique back in 1996. We also find that studies that do not account for the short-range Coulomb interaction correctly miss important feature that the Threshold Voltage standard deviations are not independent upon the position of the trap in the channel but are strongly correlated with it when the trap is located in the middle section of the source end of the channel. This suggests that an approach that correctly accounts for the short-range Coulomb interaction is a must when modeling either random dopant or random trap fluctuations in both the Threshold Voltage and the ON-current.

  • narrow width soi Devices the role of quantum mechanical size quantization effect and unintentional doping on the Device operation
    IEEE Transactions on Electron Devices, 2005
    Co-Authors: Dragica Vasileska, Shaikh Ahmed
    Abstract:

    The ultimate limits in scaling of conventional MOSFET Devices have led the researchers from all over the world to look for novel Device concepts, such as ultrathin-body (UTB) silicon-on-insulator (SOI), dual-gate SOI Devices, FinFETs, focused ion beam MOSFETs, etc. These novel Devices suppress some of the short channel effects exhibited by conventional MOSFETs. However, a lot of the old issues still remain and new issues begin to appear. For example, in UTB SOI Devices, dual-gate MOSFETs and in FinFET Devices, quantum-mechanical size quantization effects significantly affect the overall Device behavior. In addition, unintentional doping leads to considerable fluctuation in key Device parameters. In this work we investigate the role of two-dimensional quantization effects in the operation of a narrow-width SOI Device using an effective potential scheme in conjunction with a three-dimensional ensemble Monte Carlo particle-based Device simulator. We also investigate the influence of unintentional doping on the operation of this Device. We find that proper inclusion of quantization effects is needed to explain the experimentally observed width dependence of the Threshold Voltage. With regard to the problem of unintentional doping, impurities near the middle portion of the source end of the channel have most significant impact on the Device drive current and the fluctuations in the Device Threshold Voltage.

  • Role of quantization effects in the operation of ultrasmall MOSFETs and SOI Device structures
    Microelectronic Engineering, 2002
    Co-Authors: Dragica Vasileska, Richard Akis, Irena Knezevic, Srdan N. Milicić, Ahmed, David K. Ferry
    Abstract:

    The continued scaling of Devices towards the ultimate limit of 50-nm MOSFET by the year 2007 necessitates the use of higher substrate doping densities in both conventional Devices and in the alternative Device technologies. The higher substrate doping density, on the other hand, gives rise to pronounced space quantization effects that must be taken into account when modeling these novel Device structures. One way to include space quantization is via solution of the Schrodinger equation coupled to conventional drift-diffusion, hydrodynamic or Monte Carlo particle-based simulators. An alternative way is to use the recently proposed effective potential approach. In this work, we apply the effective potential approach when modeling a conventional 50-nm MOSFET Device and an SOI Device structure. For the SOI Device we also utilize the Landauer's approach to calculate the current and estimate the Device Threshold Voltage increase due to the lateral quantization.

  • Ultra-small MOSFETs: The importance of the full Coulomb interaction on Device characteristics
    VLSI Design, 2001
    Co-Authors: W.j. Gross, Dragica Vasileska, David K. Ferry
    Abstract:

    We discuss a full three-dimensional model of an ultra-small MOSFET, in which the transport is treated by a coupled EMC and molecular dynamics (MD) procedure to treat the Coulomb interaction in real space. The inclusion of the proper Coulomb interaction affects both the energy and momentum relaxation processes, but also has a dramatic effect on the characteristic curves of the Device. We find that the short-range e–e and e–i terms, combined with discrete impurity effects, is also needed for accurate measurement of the Device Threshold Voltage.

Diing Shenp Ang - One of the best experts on this subject based on the ideXlab platform.

  • The Impact of Nitrogen on the Frequency Dependence of Negative-Bias Temperature Instability
    2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007
    Co-Authors: S. Wang, Diing Shenp Ang
    Abstract:

    Negative-bias temperature instability (NBTI) of the ultra-thin oxynitride gate p-MOSFET is studied as a function of frequency under unipolar ac gate stress. Device Threshold Voltage shift |DeltaVt| is shown to exhibit an inverse power-law dependence on frequency, i.e. |DeltaVt| prop fgamma, where the exponent gamma ~ 0.042 for p-MOSFETs (A) with ~ 1.2 at. % nitrogen concentration [N] at the Si-SiO2 interface. The exponent y is observed to decrease with increased [N] (gamma ~ 0.017 for p-MOSFETs (B) with [N] ~ 4.2 at. %), indicating a much weaker NBTI frequency dependence in more heavily nitrided ultra-thin gate p-MOSFETs. Analysis shows that the weaker frequency dependence is due to the increased generation and locking-in of nitrogen-related deep-level hole traps, which suppress the recovery of the p-MOSFET. The findings reveal important implications of the nitrogen-driven NBTI mechanism on high-frequency circuit operation.

  • On the non-Arrhenius behavior of negative-bias temperature instability
    Applied Physics Letters, 2006
    Co-Authors: Diing Shenp Ang, S. Wang
    Abstract:

    Evidence from negative-bias temperature stressing of the ultrathin Si3N4∕SiOx gate p-channel field-effect transistor indicates that non-Arrhenius behavior is a consequence of the superposition of two distinct defect generation mechanisms with different power-law time dependence (tn) and activation energy (Ea). The two mechanisms are (1) a hole trapping mechanism (t0.1; Ea∼0.02eV) and (2) the classical hydrogen diffusion mechanism (t0.25; Ea∼0.2–0.3eV). When temperature increases, the latter gradually dominates, causing the exponent n, of the overall time-dependent shift of the Device Threshold Voltage (∣ΔVth∣1+2∝tn), to increase. Eliminating the contribution of the hole trapping mechanism, i.e. ∣ΔVth∣1 from overall Threshold Voltage shift consistently reproduces ∣ΔVth∣2∝tn characteristics which bear the classical signature of negative-bias temperature instability, i.e., n≈0.25 and is independent of temperature.

Anantha P Chandrakasan - One of the best experts on this subject based on the ideXlab platform.

  • a 65 nm sub v_ t microcontroller with integrated sram and switched capacitor dc dc converter
    IEEE Journal of Solid-state Circuits, 2009
    Co-Authors: Joyce Kwong, Naveen Verma, Yogesh Ramadass, Anantha P Chandrakasan
    Abstract:

    Aggressive supply Voltage scaling to below the Device Threshold Voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low Voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-Threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-Threshold cell library and timing methodology to address output Voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable Voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.

  • nanometer mosfet variation in minimum energy subThreshold circuits
    IEEE Transactions on Electron Devices, 2008
    Co-Authors: Naveen Verma, Joyce Kwong, Anantha P Chandrakasan
    Abstract:

    Minimum energy operation for digital circuits typically requires scaling the power supply below the Device Threshold Voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental Device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.