The Experts below are selected from a list of 43305 Experts worldwide ranked by ideXlab platform

Michiel Steyaert - One of the best experts on this subject based on the ideXlab platform.

  • EMI-Resistant CMOS Differential Input Stages
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    This paper studies and compares the performances of CMOS Differential input stages with a high degree of immunity against electromagnetic interferences (EMIs) and introduces a source-buffered Differential Pair which is very resistant to EMI coupled at its inputs. The EMI behavior of this source-buffered Differential-Pair topology has been evaluated with a test chip: When injecting an EMI signal of 750 mV rms at the input terminals, the measured maximal EMI-induced input offset voltage corresponds to 116 mV for the source-buffered topology compared with 610 mV for the classic Differential Pair, which constitutes a major improvement.

  • a cmos source buffered Differential input stage with high emi suppression
    European Solid-State Circuits Conference, 2008
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    This paper introduces a CMOS source-buffered Differential input stage exhibiting a high degree of immunity against electromagnetic interferences (EMI) which are applied on its input pins. The measurements of a test-IC illustrate that the source-buffered Differential Pair generates a maximal EMI induced input offset voltage of 116 mV when a 750 mV RMS EMI signal is injected in its inputs, while a classic Differential Pair output is saturated with a maximal offset of 610 mV under the same circumstances.

  • ESSCIRC - A CMOS source-buffered Differential input stage with high EMI suppression
    ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    This paper introduces a CMOS source-buffered Differential input stage exhibiting a high degree of immunity against electromagnetic interferences (EMI) which are applied on its input pins. The measurements of a test-IC illustrate that the source-buffered Differential Pair generates a maximal EMI induced input offset voltage of 116 mV when a 750 mV RMS EMI signal is injected in its inputs, while a classic Differential Pair output is saturated with a maximal offset of 610 mV under the same circumstances.

  • EMI resisting CMOS Differential Pair structure
    Electronics Letters, 2006
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    An improved Differential Pair structure, which is highly immune to conducted electromagnetic interference (EMI), is described. This new structure has a very low input offset voltage, even when a large EMI is superimposed on the nominal input signal.

Jeanmichel Redoute - One of the best experts on this subject based on the ideXlab platform.

  • EMI-Resistant CMOS Differential Input Stages
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    This paper studies and compares the performances of CMOS Differential input stages with a high degree of immunity against electromagnetic interferences (EMIs) and introduces a source-buffered Differential Pair which is very resistant to EMI coupled at its inputs. The EMI behavior of this source-buffered Differential-Pair topology has been evaluated with a test chip: When injecting an EMI signal of 750 mV rms at the input terminals, the measured maximal EMI-induced input offset voltage corresponds to 116 mV for the source-buffered topology compared with 610 mV for the classic Differential Pair, which constitutes a major improvement.

  • a cmos source buffered Differential input stage with high emi suppression
    European Solid-State Circuits Conference, 2008
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    This paper introduces a CMOS source-buffered Differential input stage exhibiting a high degree of immunity against electromagnetic interferences (EMI) which are applied on its input pins. The measurements of a test-IC illustrate that the source-buffered Differential Pair generates a maximal EMI induced input offset voltage of 116 mV when a 750 mV RMS EMI signal is injected in its inputs, while a classic Differential Pair output is saturated with a maximal offset of 610 mV under the same circumstances.

  • ESSCIRC - A CMOS source-buffered Differential input stage with high EMI suppression
    ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    This paper introduces a CMOS source-buffered Differential input stage exhibiting a high degree of immunity against electromagnetic interferences (EMI) which are applied on its input pins. The measurements of a test-IC illustrate that the source-buffered Differential Pair generates a maximal EMI induced input offset voltage of 116 mV when a 750 mV RMS EMI signal is injected in its inputs, while a classic Differential Pair output is saturated with a maximal offset of 610 mV under the same circumstances.

  • EMI resisting CMOS Differential Pair structure
    Electronics Letters, 2006
    Co-Authors: Jeanmichel Redoute, Michiel Steyaert
    Abstract:

    An improved Differential Pair structure, which is highly immune to conducted electromagnetic interference (EMI), is described. This new structure has a very low input offset voltage, even when a large EMI is superimposed on the nominal input signal.

Igor M. Filanovsky - One of the best experts on this subject based on the ideXlab platform.

  • Linear switching of the Differential Pair tail current
    IEEE Circuits and Devices Magazine, 1996
    Co-Authors: Igor M. Filanovsky
    Abstract:

    Sometimes a need arises to have two complementary currents and for this purpose one usually employs a Differential Pair. However, the conventional arrangement has the disadvantages of nonlinear control of the tail current switching and a small range of the control voltage. The author presents a circuit which eliminates this deficiency.

Hanfeng Wang - One of the best experts on this subject based on the ideXlab platform.

  • Undesired Resonances in High-Speed Differential Pair due to Non-Ideal Return Path Design
    2019 IEEE International Symposium on Electromagnetic Compatibility Signal & Power Integrity (EMC+SIPI), 2019
    Co-Authors: Yansheng Wang, Hanfeng Wang
    Abstract:

    This paper studies a specific G-S-S-G style high-speed Differential Pair. Simulation shows that resonances exist in both common- and Differential-mode signals. With the further investigation, it turns out to be that a quarter-wavelength resonant structure is incautiously created, which is responsible for the resonances. To remove the resonances, two methods are recommended in this paper. Each method has its own benefits and limitations. The proposed solutions can be treated as design rules when similar Differential Pairs are designed.

A.h.m. Van Roermund - One of the best experts on this subject based on the ideXlab platform.

  • A reduced-area low-power low-voltage single-ended Differential Pair
    IEEE Journal of Solid-State Circuits, 1997
    Co-Authors: Jan Mulder, M. Van De Gevel, A.h.m. Van Roermund
    Abstract:

    In analog very large scale integration (VLSI), a high computational density is important. Area savings can be obtained by operating the MOS transistor in the triode region, thus exploiting its symmetrical nature. Applying this theory to a single-ended Differential Pair results in an area reduction of up to a factor 1.5, which can be significant, e.g., for neural networks, where the basic cells are repeated many times on a single chip. The proposed circuit also has advantages with respect to low-power and low-voltage operation.