The Experts below are selected from a list of 16062 Experts worldwide ranked by ideXlab platform

Jeffrey Prinzie - One of the best experts on this subject based on the ideXlab platform.

  • Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits
    Electronics, 2020
    Co-Authors: Karel Appels, Jeffrey Prinzie
    Abstract:

    This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) Digital Integrated Circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) Digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

  • Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies
    Electronics, 2019
    Co-Authors: Jeffrey Prinzie, Karel Appels, S. Kulis
    Abstract:

    This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) Digital Integrated Circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

Karel Appels - One of the best experts on this subject based on the ideXlab platform.

  • Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits
    Electronics, 2020
    Co-Authors: Karel Appels, Jeffrey Prinzie
    Abstract:

    This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) Digital Integrated Circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) Digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

  • Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies
    Electronics, 2019
    Co-Authors: Jeffrey Prinzie, Karel Appels, S. Kulis
    Abstract:

    This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) Digital Integrated Circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

S. Kulis - One of the best experts on this subject based on the ideXlab platform.

  • Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies
    Electronics, 2019
    Co-Authors: Jeffrey Prinzie, Karel Appels, S. Kulis
    Abstract:

    This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) Digital Integrated Circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

Michael R. Melloch - One of the best experts on this subject based on the ideXlab platform.

  • Monolithic CMOS Digital Integrated Circuits in 6H-SiC using an implanted p-well process
    IEEE Electron Device Letters, 1997
    Co-Authors: Sei-hyung Ryu, Kevin T. Kornegay, J.a. Cooper, Michael R. Melloch
    Abstract:

    We report the first p-well Complementary Metal Oxide Semiconductor (CMOS) Digital Integrated Circuits in 6H-SiC. Enhancement mode NMOSFET's and PMOSFET's are fabricated on implanted p-wells and n-type epilayers, respectively. CMOS logic Circuits such as inverters, NAND, NOR, XOR, flip-flops, half adders, and 11-stage ring oscillators are implemented using these devices and operated at room temperature, The inverters show stable operation at room temperature and 300/spl deg/C with V/sub dd/=10 and 15 V.

  • monolithic nmos Digital Integrated Circuits in 6h sic
    IEEE Electron Device Letters, 1994
    Co-Authors: W Xie, J.a. Cooper, Michael R. Melloch
    Abstract:

    We report the first Digital monolithic Integrated Circuits in the wide bandgap semiconductor silicon carbide (SiC). These logic gates are implemented in enhancement-mode NMOS using ion implanted MOSFET's with non-self-aligned metal gates. We have fabricated and characterized inverters, NAND and NOR gates, XNOR gates, D-latches, RS flip-flops, binary counters, and half adders. All Circuits operate properly from room temperature to over 300/spl deg/C. >

Chandu Visweswariah - One of the best experts on this subject based on the ideXlab platform.

  • statistical timing for parametric yield prediction of Digital Integrated Circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
    Co-Authors: J A G Jess, Kerim Kalafala, S R Naidu, Ralph H J M Otten, Chandu Visweswariah
    Abstract:

    Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of Digital Integrated Circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results

  • statistical timing for parametric yield prediction of Digital Integrated Circuits
    Design Automation Conference, 2003
    Co-Authors: J A G Jess, Kerim Kalafala, S R Naidu, Ralph H J M Otten, Chandu Visweswariah
    Abstract:

    Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of Digital Integrated Circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by EinsTimer's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and V/sub dd/ variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.

  • DAC - Statistical timing for parametric yield prediction of Digital Integrated Circuits
    Proceedings of the 40th conference on Design automation - DAC '03, 2003
    Co-Authors: J A G Jess, Kerim Kalafala, S R Naidu, Ralph H J M Otten, Chandu Visweswariah
    Abstract:

    Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of Digital Integrated Circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by EinsTimer's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and V/sub dd/ variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.