The Experts below are selected from a list of 12381 Experts worldwide ranked by ideXlab platform
Ali Asghar Orouji - One of the best experts on this subject based on the ideXlab platform.
-
controlled kink effect in a novel high voltage ldmos transistor by creating local minimum in energy band diagram
IEEE Transactions on Electron Devices, 2017Co-Authors: Mahsa Mehrad, Meysam Zareiee, Ali Asghar OroujiAbstract:A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source Region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and Drain Regions. The modified source Region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified Drain Region causes high breakdown voltage (462 V) and low specific on-resistance ( $5.1~\text {m}\Omega \cdot ~\text {cm}^{{{{2}}}})$ . Also, the drift Region with lower doping density than Drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance.
-
controlled kink effect in a novel high voltage ldmos transistor by creating local minimum in energy band diagram
IEEE Transactions on Electron Devices, 2017Co-Authors: Mahsa Mehrad, Meysam Zareiee, Ali Asghar OroujiAbstract:A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source Region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and Drain Regions. The modified source Region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified Drain Region causes high breakdown voltage (462 V) and low specific on-resistance ( $5.1~\text {m}\Omega \cdot ~\text {cm}^{{{{2}}}})$ . Also, the drift Region with lower doping density than Drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance.
Jaechul Park - One of the best experts on this subject based on the ideXlab platform.
-
high performance amorphous oxide thin film transistors with self aligned top gate structure
International Electron Devices Meeting, 2009Co-Authors: Jaechul Park, Yong Woo Jeon, Youngsoo Park, Sanghun Jeon, Sungho Park, Hun I Song, In U Chung, Keewon KwonAbstract:We have demonstrated self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays. The processes such as source/Drain and channel engineering have been developed to realize the self-aligned top gate structure. Ar plasma is exposed on the source/Drain Region of active layer to minimize the source/Drain series resistances. To prevent the conductive channel, N 2 O plasma is also treated on the channel Region of active layer. We obtain a field effect mobility of 5.5 cm2/V·s, a threshold voltage of 1.1 V, and a sub-threshold swing of 0.35 V/decade at sub-micron a-GIZO TFTs with the length of 0.67#x00B5;m. Furthermore, a-IZO TFTs fabricated for gate and data driver circuits on glass substrate exhibit excellent electrical properties such as a field effect mobility of 115 cm2/V·s, a threshold voltage of 0.2 V, a sub-threshold swing of 0.2 V/decade, and low threshold voltage shift less than 1 V under bias temperature stress for 3 hr.
-
source Drain formation of self aligned top gate amorphous gainzno thin film transistors by hbox nh _ 3 plasma treatment
IEEE Electron Device Letters, 2009Co-Authors: Sangwook Kim, Jaechul Park, Sungho Park, Changjung Kim, Ihun Song, Sunil Kim, Huaxiang Yin, Hyungik Lee, Eunha Lee, Youngsoo ParkAbstract:The source/Drain Region of amorphous GaInZnO thin-film transistor with self-aligned top-gate structure was defined by simple NH3 plasma treatment instead of complicated processes, such as ion implantation and activation. When the source/Drain Region of active layer was exposed to NH3 gas plasma, the series resistance of the transistor decreased considerably. It exhibited electrical properties, such as a field-effect mobility of 6 cm2/V middots, a threshold voltage of 0.21 V, and a subthreshold swing of 0.23 V/dec.
-
self aligned top gate amorphous gallium indium zinc oxide thin film transistors
Applied Physics Letters, 2008Co-Authors: Jaechul Park, Sangwook Kim, Changjung Kim, Ihun Song, Sunil Kim, Huaxiang Yin, Hyungik Lee, Eunha Lee, Jaecheol Lee, K KimAbstract:We have demonstrated a self-aligned top-gate amorphous gallium indium zinc oxide thin film transistor (a-GIZO TFT). It had a field effect mobility of 5 cm2/V s, a threshold voltage of 0.2 V, and a subthreshold swing of 0.2 V/decade. Ar plasma was treated on the source/Drain Region of the a-GIZO active layer to reduce the series resistance. After Ar plasma treatment, the surface of the source/Drain Region was divided into In-rich and In-deficient Regions. The a-GIZO TFT also had a constant sheet resistance of 1 kΩ/◻ for a film thickness of over 40 nm. The interface between the source/Drain Mo metal and the Ar plasma-treated a-GIZO indicated a good Ohmic contact and a contact resistivity of 50 μΩ cm2.
Mahsa Mehrad - One of the best experts on this subject based on the ideXlab platform.
-
controlled kink effect in a novel high voltage ldmos transistor by creating local minimum in energy band diagram
IEEE Transactions on Electron Devices, 2017Co-Authors: Mahsa Mehrad, Meysam Zareiee, Ali Asghar OroujiAbstract:A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source Region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and Drain Regions. The modified source Region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified Drain Region causes high breakdown voltage (462 V) and low specific on-resistance ( $5.1~\text {m}\Omega \cdot ~\text {cm}^{{{{2}}}})$ . Also, the drift Region with lower doping density than Drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance.
-
controlled kink effect in a novel high voltage ldmos transistor by creating local minimum in energy band diagram
IEEE Transactions on Electron Devices, 2017Co-Authors: Mahsa Mehrad, Meysam Zareiee, Ali Asghar OroujiAbstract:A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source Region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and Drain Regions. The modified source Region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified Drain Region causes high breakdown voltage (462 V) and low specific on-resistance ( $5.1~\text {m}\Omega \cdot ~\text {cm}^{{{{2}}}})$ . Also, the drift Region with lower doping density than Drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance.
Sangwook Kim - One of the best experts on this subject based on the ideXlab platform.
-
source Drain formation of self aligned top gate amorphous gainzno thin film transistors by hbox nh _ 3 plasma treatment
IEEE Electron Device Letters, 2009Co-Authors: Sangwook Kim, Jaechul Park, Sungho Park, Changjung Kim, Ihun Song, Sunil Kim, Huaxiang Yin, Hyungik Lee, Eunha Lee, Youngsoo ParkAbstract:The source/Drain Region of amorphous GaInZnO thin-film transistor with self-aligned top-gate structure was defined by simple NH3 plasma treatment instead of complicated processes, such as ion implantation and activation. When the source/Drain Region of active layer was exposed to NH3 gas plasma, the series resistance of the transistor decreased considerably. It exhibited electrical properties, such as a field-effect mobility of 6 cm2/V middots, a threshold voltage of 0.21 V, and a subthreshold swing of 0.23 V/dec.
-
self aligned top gate amorphous gallium indium zinc oxide thin film transistors
Applied Physics Letters, 2008Co-Authors: Jaechul Park, Sangwook Kim, Changjung Kim, Ihun Song, Sunil Kim, Huaxiang Yin, Hyungik Lee, Eunha Lee, Jaecheol Lee, K KimAbstract:We have demonstrated a self-aligned top-gate amorphous gallium indium zinc oxide thin film transistor (a-GIZO TFT). It had a field effect mobility of 5 cm2/V s, a threshold voltage of 0.2 V, and a subthreshold swing of 0.2 V/decade. Ar plasma was treated on the source/Drain Region of the a-GIZO active layer to reduce the series resistance. After Ar plasma treatment, the surface of the source/Drain Region was divided into In-rich and In-deficient Regions. The a-GIZO TFT also had a constant sheet resistance of 1 kΩ/◻ for a film thickness of over 40 nm. The interface between the source/Drain Mo metal and the Ar plasma-treated a-GIZO indicated a good Ohmic contact and a contact resistivity of 50 μΩ cm2.
Youngsoo Park - One of the best experts on this subject based on the ideXlab platform.
-
high performance amorphous oxide thin film transistors with self aligned top gate structure
International Electron Devices Meeting, 2009Co-Authors: Jaechul Park, Yong Woo Jeon, Youngsoo Park, Sanghun Jeon, Sungho Park, Hun I Song, In U Chung, Keewon KwonAbstract:We have demonstrated self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays. The processes such as source/Drain and channel engineering have been developed to realize the self-aligned top gate structure. Ar plasma is exposed on the source/Drain Region of active layer to minimize the source/Drain series resistances. To prevent the conductive channel, N 2 O plasma is also treated on the channel Region of active layer. We obtain a field effect mobility of 5.5 cm2/V·s, a threshold voltage of 1.1 V, and a sub-threshold swing of 0.35 V/decade at sub-micron a-GIZO TFTs with the length of 0.67#x00B5;m. Furthermore, a-IZO TFTs fabricated for gate and data driver circuits on glass substrate exhibit excellent electrical properties such as a field effect mobility of 115 cm2/V·s, a threshold voltage of 0.2 V, a sub-threshold swing of 0.2 V/decade, and low threshold voltage shift less than 1 V under bias temperature stress for 3 hr.
-
source Drain formation of self aligned top gate amorphous gainzno thin film transistors by hbox nh _ 3 plasma treatment
IEEE Electron Device Letters, 2009Co-Authors: Sangwook Kim, Jaechul Park, Sungho Park, Changjung Kim, Ihun Song, Sunil Kim, Huaxiang Yin, Hyungik Lee, Eunha Lee, Youngsoo ParkAbstract:The source/Drain Region of amorphous GaInZnO thin-film transistor with self-aligned top-gate structure was defined by simple NH3 plasma treatment instead of complicated processes, such as ion implantation and activation. When the source/Drain Region of active layer was exposed to NH3 gas plasma, the series resistance of the transistor decreased considerably. It exhibited electrical properties, such as a field-effect mobility of 6 cm2/V middots, a threshold voltage of 0.21 V, and a subthreshold swing of 0.23 V/dec.
