The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Denis Flandre - One of the best experts on this subject based on the ideXlab platform.
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on the mosfet threshold Voltage extraction by transconductance and transconductance to current ratio change methods part ii effect of Drain Voltage
IEEE Transactions on Electron Devices, 2011Co-Authors: Tamara Rudenko, Valeriya Kilchytska, M Md K Arshad, Jeanpierre Raskin, A N Nazarov, Denis FlandreAbstract:In this paper, we study the effect of the Drain Voltage on the threshold Voltage extraction in long-channel MOSFETs by the transconductance change and transconductance-to-current ratio change methods, using analytical modeling and experimental data obtained on advanced UTB SOI MOSFETs. It is shown that, although these two methods have the same physical background, they feature radically different behaviors with respect to the Drain Voltage effect. In particular, the transconductance change method yields a threshold Voltage value, which regularly increases with Drain Voltage, and interpretation, as well as analytical expression for this dependence, is provided. In contrast, for the transconductance-to-current ratio change method, the increase of the extracted threshold Voltage value with Drain Voltage is smaller and rapidly saturates; hence, the threshold Voltage extraction is more stable and reliable. Modeling derivations are found to be in excellent agreement with measurements on long-channel UTB SOI MOSFETs as well as 2-D simulations.
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Influence of Drain Voltage on MOSFET threshold Voltage determination by transconductance change and gm/Id methods
Ulis 2011 Ultimate Integration on Silicon, 2011Co-Authors: Tamara Rudenko, Valeriya Kilchytska, M Md K Arshad, J.-p. Raskin, A. Nazarov, Denis FlandreAbstract:In this work, we study the effect of the Drain Voltage on the threshold Voltage extraction in long-channel MOSFETs by the transconductance and transconductance-to-current-ratio change methods, using analytical modeling and experimental data obtained on UTB SOI MOSFETs.
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Influence of Drain Voltage on MOSFET threshold Voltage determination by transconductance change and g m /I d methods
Ulis 2011 Ultimate Integration on Silicon, 2011Co-Authors: Tamara Rudenko, Valeriya Kilchytska, J.-p. Raskin, A. Nazarov, M. K. Md Arshad, Denis FlandreAbstract:In this work, we study the effect of the Drain Voltage on the threshold Voltage extraction in long-channel MOSFETs by the transconductance and transconductance-to-current-ratio change methods, using analytical modeling and experimental data obtained on UTB SOI MOSFETs.
Yasuo Arai - One of the best experts on this subject based on the ideXlab platform.
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super steep subthreshold slope pn body tied soi fet s of ultra low Drain Voltage 0 1v with body bias below 1 0v
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2016Co-Authors: Takahiro Yoshida, Takashi Horii, Masao Okihara, Yasuo AraiAbstract:It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFET's which show the super steep SS with the ultralow Drain Voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N−. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.
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Super steep subthreshold slope PN-body tied SOI FET's of ultra low Drain Voltage=0.1V with body bias below 1.0V
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016Co-Authors: Takahiro Yoshida, Takashi Horii, Masao Okihara, Yasuo AraiAbstract:It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFET's which show the super steep SS with the ultralow Drain Voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N-. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.
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super steep subthreshold slope pn body tied soi fet with ultra low Drain Voltage down to 0 1v
International Electron Devices Meeting, 2015Co-Authors: Takayuki Mori, Yousuke Kuramoto, Takashi Horii, Takahiro Yoshida, Kazuma Takeda, Hiroki Kasai, Masao Okihara, Yasuo AraiAbstract:We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and Drain (S/D) structure. The device shows a super steep SS (<6mV/dec) over 3 decades of the Drain current with an ultralow Drain Voltage down to 0.1V. It also shows a low leakage current (below 1pA/um), a good Id-Vd characteristic and a negligible hysteresis characteristic.
J.r. Davis - One of the best experts on this subject based on the ideXlab platform.
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Degradation in thin-film SOI MOSFET's caused by single-transistor latch
IEEE Electron Device Letters, 1990Co-Authors: R.j.t. Bunyan, M.j. Uren, N.j. Thomas, J.r. DavisAbstract:The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and Drain, the minimum Drain Voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the Drain. Consequently, the maximum allowable Drain Voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET.
Tamara Rudenko - One of the best experts on this subject based on the ideXlab platform.
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on the mosfet threshold Voltage extraction by transconductance and transconductance to current ratio change methods part ii effect of Drain Voltage
IEEE Transactions on Electron Devices, 2011Co-Authors: Tamara Rudenko, Valeriya Kilchytska, M Md K Arshad, Jeanpierre Raskin, A N Nazarov, Denis FlandreAbstract:In this paper, we study the effect of the Drain Voltage on the threshold Voltage extraction in long-channel MOSFETs by the transconductance change and transconductance-to-current ratio change methods, using analytical modeling and experimental data obtained on advanced UTB SOI MOSFETs. It is shown that, although these two methods have the same physical background, they feature radically different behaviors with respect to the Drain Voltage effect. In particular, the transconductance change method yields a threshold Voltage value, which regularly increases with Drain Voltage, and interpretation, as well as analytical expression for this dependence, is provided. In contrast, for the transconductance-to-current ratio change method, the increase of the extracted threshold Voltage value with Drain Voltage is smaller and rapidly saturates; hence, the threshold Voltage extraction is more stable and reliable. Modeling derivations are found to be in excellent agreement with measurements on long-channel UTB SOI MOSFETs as well as 2-D simulations.
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Influence of Drain Voltage on MOSFET threshold Voltage determination by transconductance change and gm/Id methods
Ulis 2011 Ultimate Integration on Silicon, 2011Co-Authors: Tamara Rudenko, Valeriya Kilchytska, M Md K Arshad, J.-p. Raskin, A. Nazarov, Denis FlandreAbstract:In this work, we study the effect of the Drain Voltage on the threshold Voltage extraction in long-channel MOSFETs by the transconductance and transconductance-to-current-ratio change methods, using analytical modeling and experimental data obtained on UTB SOI MOSFETs.
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Influence of Drain Voltage on MOSFET threshold Voltage determination by transconductance change and g m /I d methods
Ulis 2011 Ultimate Integration on Silicon, 2011Co-Authors: Tamara Rudenko, Valeriya Kilchytska, J.-p. Raskin, A. Nazarov, M. K. Md Arshad, Denis FlandreAbstract:In this work, we study the effect of the Drain Voltage on the threshold Voltage extraction in long-channel MOSFETs by the transconductance and transconductance-to-current-ratio change methods, using analytical modeling and experimental data obtained on UTB SOI MOSFETs.
Kevin J. Chen - One of the best experts on this subject based on the ideXlab platform.
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OFF-state Drain-Voltage-stress-induced VTH Instability in Schottky-type p-GaN Gate HEMTs
IEEE Journal of Emerging and Selected Topics in Power Electronics, 1Co-Authors: Junting Chen, Jiabei He, Chengcai Wang, Zheyang Zheng, Kevin J. ChenAbstract:In this paper, we systematically investigate the OFF-state Drain-Voltage-stress-induced threshold Voltage (VTH) instability in Schottky-type p-GaN gate high electron mobility transistors (HEMTs). OFF-state Drain-Voltage stress and recovery tests were conducted under various temperatures and different Drain biases. A sharp increase in VTH was observed at the beginning of the stress, and VTH kept shifting positively during the stress until it reached saturation. Further experiments showed that two different mechanisms dominated the VTH shift, which were distinguished by the temperature dependence, degradation/ recovery process and affected locations in the gate region. The hole deficiency caused by hole emission from the p-GaN layer is suggested to be the dominant reason for the VTH instability at the beginning of the stress, while with increasing stress time, electron trapping in the barrier and buffer layers gradually dominates the VTH shift. Based on the identified mechanisms, physics-based analytical calculations and empirical fitting are conducted to describe the VTH behavior during the OFF-state Drain-Voltage stress. The fundamental mechanisms can provide a guide to develop corresponding methods to address the Drain-induced VTH instability issue.
