The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
J L Prince - One of the best experts on this subject based on the ideXlab platform.
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application specific cmos output Driver Circuit design techniques to reduce simultaneous switching noise
IEEE Journal of Solid-state Circuits, 1993Co-Authors: R Senthinathan, J L PrinceAbstract:Application specific CMOS Circuit design techniques to reduce simultaneous switching noise (SSN-also known as Delta-I noise or ground bounce) were analyzed. Detailed investigation on the CMOS output Driver switching current components was performed. The limitations in using current controlled (CC) CMOS output Drivers in high-speed (>30 MHz) design applications are explained. Application specific, high-speed, controlled slew rate (CSR) CMOS output Drivers were studied and designed. For a given device channel length, once the preDriver and Driver device sizes are fixed, the performance (speed, switching noise, sink/source capabilities) is determined. With controlled slew rate output Drivers, more than 50% improvement was found in the input receiver noise immunity (measure of maximum tolerable SSN) compared to conventional Drivers, while the speed and sink/source capabilities are preserved. This effective SSN reduction improvement is achieved with only a small increase in output Driver silicon area. The CSR output Driver uses distributed and weighted switching Driver segments to control the output Driver's slew rate for a given load-capacitance. These CSR CMOS output Drivers were compared with standard CMOS output Drivers, showing significant reduction in effective switching noise pulse width. >
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noise immunity characteristics of cmos receivers and effects of skewing damping cmos output Driver switching waveform on the simultaneous switching noise
Microelectronics Journal, 1992Co-Authors: R Senthinathan, J L Prince, S NimmagaddaAbstract:Abstract A detailed study of the characteristics of CMOS receiver noise immunity and the effects of skewing CMOS output Drivers on simultaneous switching noise was performed. Closed-form equations are given to calculate the simultaneous switching noise and the number of V DD /V SS bond pads-packagem pins in multichip modules. Guidelines for grouping and optimal skewing of CMOS output Drivers to reduce the total effective power/ground noise are discussed. Performance trade-offs in using an additional damping resistor in the output Driver Circuit to reduce power/ground noise were analyzed. Design curves are given to minimize the ‘effective’ switching noise without much trade-off in output Driver speed.
R Senthinathan - One of the best experts on this subject based on the ideXlab platform.
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application specific cmos output Driver Circuit design techniques to reduce simultaneous switching noise
IEEE Journal of Solid-state Circuits, 1993Co-Authors: R Senthinathan, J L PrinceAbstract:Application specific CMOS Circuit design techniques to reduce simultaneous switching noise (SSN-also known as Delta-I noise or ground bounce) were analyzed. Detailed investigation on the CMOS output Driver switching current components was performed. The limitations in using current controlled (CC) CMOS output Drivers in high-speed (>30 MHz) design applications are explained. Application specific, high-speed, controlled slew rate (CSR) CMOS output Drivers were studied and designed. For a given device channel length, once the preDriver and Driver device sizes are fixed, the performance (speed, switching noise, sink/source capabilities) is determined. With controlled slew rate output Drivers, more than 50% improvement was found in the input receiver noise immunity (measure of maximum tolerable SSN) compared to conventional Drivers, while the speed and sink/source capabilities are preserved. This effective SSN reduction improvement is achieved with only a small increase in output Driver silicon area. The CSR output Driver uses distributed and weighted switching Driver segments to control the output Driver's slew rate for a given load-capacitance. These CSR CMOS output Drivers were compared with standard CMOS output Drivers, showing significant reduction in effective switching noise pulse width. >
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noise immunity characteristics of cmos receivers and effects of skewing damping cmos output Driver switching waveform on the simultaneous switching noise
Microelectronics Journal, 1992Co-Authors: R Senthinathan, J L Prince, S NimmagaddaAbstract:Abstract A detailed study of the characteristics of CMOS receiver noise immunity and the effects of skewing CMOS output Drivers on simultaneous switching noise was performed. Closed-form equations are given to calculate the simultaneous switching noise and the number of V DD /V SS bond pads-packagem pins in multichip modules. Guidelines for grouping and optimal skewing of CMOS output Drivers to reduce the total effective power/ground noise are discussed. Performance trade-offs in using an additional damping resistor in the output Driver Circuit to reduce power/ground noise were analyzed. Design curves are given to minimize the ‘effective’ switching noise without much trade-off in output Driver speed.
Sei Hyung Ryu - One of the best experts on this subject based on the ideXlab platform.
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A Silicon Carbide CMOS Intelligent Gate Driver Circuit with Stable Operation over a Wide Temperature Range
IEEE Journal of Solid-State Circuits, 1999Co-Authors: Jian-song Chen, Kevin T. Kornegay, Sei Hyung RyuAbstract:In this paper, we present the design and fabrication of a high-temperature silicon carbide CMOS intelligent gate Driver Circuit intended for high-power switching applications. Using a temperature-insensitive comparator, several functions including overvoltage and undervoltage, as well as short- and open-load detection, are provided, all of which are operational up to 300 deg;C. These integrated Circuits are ideally suited for harsh and high-temperature environments such as automotive and aircraft jet engines
J B Kuo - One of the best experts on this subject based on the ideXlab platform.
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energy efficient cmos large load Driver Circuit with the complementary adiabatic bootstrap cab technique for low power tft lcd system applications
International Symposium on Circuits and Systems, 2005Co-Authors: G Y Liu, N C Wang, J B KuoAbstract:This paper reports an energy-efficient CMOS large-load Driver Circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications. Using two differential inputs and via dual paths for bootstrap and energy recovery to V/sub DD//ground, this CAB load Driver with an output load of 30 pF and operating at 5 V, provides a high-speed performance, consuming 60% less power as compared to the adiabatic/bootstrapped Driver with single-path for bootstrap and energy recovery.
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a 1 5 v full swing bootstrapped cmos large capacitive load Driver Circuit suitable for low voltage cmos vlsi
IEEE Journal of Solid-state Circuits, 1997Co-Authors: J H Lou, J B KuoAbstract:This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load Driver Circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS Driver Circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS Driver Circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load Driver Circuit is still advantageous.
Yan Cun Li - One of the best experts on this subject based on the ideXlab platform.
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A novel single-stage high-power-factor AC-to-DC LED driving Circuit with leakage inductance energy recycling
IEEE Transactions on Industrial Electronics, 2012Co-Authors: Yan Cun LiAbstract:This paper proposes a novel single-stage ac-to-dc light-emitting-diode (LED) Driver Circuit. A buck–boost power factor (PF) corrector is integrated with a flyback converter. A recycling path is built to recover the inductive leakage energy. In this way, the presented Circuit can provide not only high PF and low total harmonic distortion but also high conversion efficiency and low switching voltage spikes. Above 0.95 PF and 90% efficiency are obtained from an 8-W LED lamp Driver prototype.
