The Experts below are selected from a list of 771 Experts worldwide ranked by ideXlab platform
Young Ho Kwak - One of the best experts on this subject based on the ideXlab platform.
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a 120 mhz 1 8 ghz cmos dll based clock generator for Dynamic Frequency Scaling
IEEE Journal of Solid-state Circuits, 2006Co-Authors: Young Ho KwakAbstract:A delay-locked loop (DLL)-based clock generator for Dynamic Frequency Scaling has been developed in a 0.35-mum CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the Frequency Dynamically in a short time. If the clock generator scales its output Frequency Dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of plusmn6.6 ps at 1.3 GHz
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a cmos dll based 120mhz to 1 8ghz clock generator for Dynamic Frequency Scaling
International Solid-State Circuits Conference, 2005Co-Authors: Young Ho Kwak, Seokryung YoonAbstract:A DLL-based clock generator for Dynamic Frequency Scaling is fabricated in a 0.35 /spl mu/m CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The Frequency can be Dynamically changed. If the clock generator scales its output Frequency Dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of /spl plusmn/6.6ps/sub pp/ at 1.3GHz.
Kyunghoon Chung - One of the best experts on this subject based on the ideXlab platform.
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an antiharmonic programmable dll based Frequency multiplier for Dynamic Frequency Scaling
IEEE Transactions on Very Large Scale Integration Systems, 2010Co-Authors: Sunghwa Ok, Kyunghoon ChungAbstract:This paper describes a new delay-locked loop (DLL)-based Frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the Frequency multiplication. The antiharmonic DLL-based Frequency multiplier, implemented in a 0.18-μ.m CMOS process, occupies an active area of 0.043 mm2, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.
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an anti harmonic programmable dll based Frequency multiplier for Dynamic Frequency Scaling
Asian Solid-State Circuits Conference, 2007Co-Authors: Kyunghoon ChungAbstract:This paper describes a new delay-locked loop (DLL) based Frequency multiplier which includes a lock controller and a PD to prevent false locking and increase locking range relative to conventional DLLs. By using multiple clock phase of the DLL, the lock controller detects whether the VCDL delay is within a correct locking range or not. A differentially controlled edge combiner for Frequency multiplication is also proposed. The anti-harmonic DM-based Frequency multiplier implemented in a 0.18 μm CMOS technology occupies an active area of 0.043 mm* and dissipates 36.7 mW at 1.7GHz. output clock. The measured RMS and peak-to-peak jitters for the multiplied output clock at 1.7GHz. are 2.64ps and 16.8ps, respectively.
Sunghwa Ok - One of the best experts on this subject based on the ideXlab platform.
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an antiharmonic programmable dll based Frequency multiplier for Dynamic Frequency Scaling
IEEE Transactions on Very Large Scale Integration Systems, 2010Co-Authors: Sunghwa Ok, Kyunghoon ChungAbstract:This paper describes a new delay-locked loop (DLL)-based Frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the Frequency multiplication. The antiharmonic DLL-based Frequency multiplier, implemented in a 0.18-μ.m CMOS process, occupies an active area of 0.043 mm2, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.
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A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2009Co-Authors: Sunghwa OkAbstract:A delay-locked-loop (DLL)-based clock generator for Dynamic Frequency Scaling has been developed in a 0.13-mum CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the Frequency Dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to Frequency of the proposed clock generator is smaller than those of conventional ones.
Tudor Cioara - One of the best experts on this subject based on the ideXlab platform.
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ICCP - Time series based Dynamic Frequency Scaling solution for optimizing the CPU energy consumption
2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, 2011Co-Authors: Tudor Cioara, Georgiana Copil, Daniel Moldovan, Ionut Anghel, Ioan Salomie, Marius GrindeanAbstract:In this paper the problem of service center servers high energy consumption is tackled by proposing a time series based CPU Dynamic Frequency Scaling algorithm. The algorithm senses the workload changes and adapts the CPU power states thus minimizing the CPU energy consumption. Our solution analyzes the CPU workload time series for identifying the frequent workload patterns. For each frequent pattern, the corresponding Dynamic Frequency Scaling actions are determined and associated using information about the pattern's sub-sequences trends. A workload characterization function is defined and used to identify the pattern trends. To identify the membership of the new CPU workload observations to a frequent CPU workload pattern, a sliding window based method is used. If such a match is found, the Dynamic Frequency Scaling actions associated to the frequent pattern are executed and the pattern occurrence probability is increased.
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ICCP - Dynamic Frequency Scaling algorithms for improving the CPU's energy efficiency
2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, 2011Co-Authors: Ionut Anghel, Georgiana Copil, Tudor Cioara, Ioan Salomie, Daniel MoldovanAbstract:This paper approaches the problem of improving the service center server CPU's energy efficiency by executing Dynamic Frequency Scaling actions and performing tradeoffs between CPU's computational performance and its power consumption. Two different algorithms are designed and implemented: an immune inspired algorithm and a fuzzy logic based algorithm. The immune inspired algorithm uses the human antigen as a model to represent the server power / performance state. Using a set of detectors the antigens are classified as self for optimal power consumption state or non-self for non-optimal power consumption state. For the non-self antigens a biologically inspired clonal selection approach is used to determine the actions that need to be executed to bring the server's CPU in an optimal power consumption state. The fuzzy logic based algorithm adaptively changes the processor performance states to the incoming workload. The algorithm also filters workload spikes because frequent p-states transition costs can outweigh the benefit of adaptation.
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Time series based Dynamic Frequency Scaling solution for optimizing the CPU energy consumption
2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, 2011Co-Authors: Tudor Cioara, Georgiana Copil, Daniel Moldovan, Ionut Anghel, Ioan Salomie, Marius GrindeanAbstract:In this paper the problem of service center servers high energy consumption is tackled by proposing a time series based CPU Dynamic Frequency Scaling algorithm. The algorithm senses the workload changes and adapts the CPU power states thus minimizing the CPU energy consumption. Our solution analyzes the CPU workload time series for identifying the frequent workload patterns. For each frequent pattern, the corresponding Dynamic Frequency Scaling actions are determined and associated using information about the pattern's sub-sequences trends. A workload characterization function is defined and used to identify the pattern trends. To identify the membership of the new CPU workload observations to a frequent CPU workload pattern, a sliding window based method is used. If such a match is found, the Dynamic Frequency Scaling actions associated to the frequent pattern are executed and the pattern occurrence probability is increased.
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Dynamic Frequency Scaling Algorithms for ,PSURYLQJWKH&38∂V(QHUJ\(IILFLHQF\
2011Co-Authors: Ionut Anghel, Georgiana Copil, Tudor Cioara, Ioan Salomie, Daniel MoldovanAbstract:This paper approaches the problem of improving the service center VHUYHUV� &38∂VHQHUJ\� HIILFLHQF\� E\� executing Dynamic Frequency Scaling actions and performing tradeoffs EHWZHHQ� &38∂VFRPSXWDWLRQDOSHUIRUPDQFHDQGLWV� power consumption. Two different algorithms are designed and implemented: an immune inspired algorithm and a fuzzy logic based algorithm. The immune inspired algorithm uses the human antigen as a model to represent the server power / performance state. Using a set of detectors the antigens are classified as self for optimal power consumption state or non-self for non-optimal power consumption state. For the non-self antigens a biologically inspired clonal selection approach is used to determine the actions that need to be executed to bring the server∂V�&38� in an optimal power consumption state. The fuzzy logic based algorithm adaptively changes the processor performance states to the incoming workload. The algorithm also filters workload spikes because frequent p-states transition costs can outweigh the benefit of adaptation.
Daniel Moldovan - One of the best experts on this subject based on the ideXlab platform.
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ICCP - Time series based Dynamic Frequency Scaling solution for optimizing the CPU energy consumption
2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, 2011Co-Authors: Tudor Cioara, Georgiana Copil, Daniel Moldovan, Ionut Anghel, Ioan Salomie, Marius GrindeanAbstract:In this paper the problem of service center servers high energy consumption is tackled by proposing a time series based CPU Dynamic Frequency Scaling algorithm. The algorithm senses the workload changes and adapts the CPU power states thus minimizing the CPU energy consumption. Our solution analyzes the CPU workload time series for identifying the frequent workload patterns. For each frequent pattern, the corresponding Dynamic Frequency Scaling actions are determined and associated using information about the pattern's sub-sequences trends. A workload characterization function is defined and used to identify the pattern trends. To identify the membership of the new CPU workload observations to a frequent CPU workload pattern, a sliding window based method is used. If such a match is found, the Dynamic Frequency Scaling actions associated to the frequent pattern are executed and the pattern occurrence probability is increased.
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ICCP - Dynamic Frequency Scaling algorithms for improving the CPU's energy efficiency
2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, 2011Co-Authors: Ionut Anghel, Georgiana Copil, Tudor Cioara, Ioan Salomie, Daniel MoldovanAbstract:This paper approaches the problem of improving the service center server CPU's energy efficiency by executing Dynamic Frequency Scaling actions and performing tradeoffs between CPU's computational performance and its power consumption. Two different algorithms are designed and implemented: an immune inspired algorithm and a fuzzy logic based algorithm. The immune inspired algorithm uses the human antigen as a model to represent the server power / performance state. Using a set of detectors the antigens are classified as self for optimal power consumption state or non-self for non-optimal power consumption state. For the non-self antigens a biologically inspired clonal selection approach is used to determine the actions that need to be executed to bring the server's CPU in an optimal power consumption state. The fuzzy logic based algorithm adaptively changes the processor performance states to the incoming workload. The algorithm also filters workload spikes because frequent p-states transition costs can outweigh the benefit of adaptation.
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Time series based Dynamic Frequency Scaling solution for optimizing the CPU energy consumption
2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, 2011Co-Authors: Tudor Cioara, Georgiana Copil, Daniel Moldovan, Ionut Anghel, Ioan Salomie, Marius GrindeanAbstract:In this paper the problem of service center servers high energy consumption is tackled by proposing a time series based CPU Dynamic Frequency Scaling algorithm. The algorithm senses the workload changes and adapts the CPU power states thus minimizing the CPU energy consumption. Our solution analyzes the CPU workload time series for identifying the frequent workload patterns. For each frequent pattern, the corresponding Dynamic Frequency Scaling actions are determined and associated using information about the pattern's sub-sequences trends. A workload characterization function is defined and used to identify the pattern trends. To identify the membership of the new CPU workload observations to a frequent CPU workload pattern, a sliding window based method is used. If such a match is found, the Dynamic Frequency Scaling actions associated to the frequent pattern are executed and the pattern occurrence probability is increased.
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Dynamic Frequency Scaling Algorithms for ,PSURYLQJWKH&38∂V(QHUJ\(IILFLHQF\
2011Co-Authors: Ionut Anghel, Georgiana Copil, Tudor Cioara, Ioan Salomie, Daniel MoldovanAbstract:This paper approaches the problem of improving the service center VHUYHUV� &38∂VHQHUJ\� HIILFLHQF\� E\� executing Dynamic Frequency Scaling actions and performing tradeoffs EHWZHHQ� &38∂VFRPSXWDWLRQDOSHUIRUPDQFHDQGLWV� power consumption. Two different algorithms are designed and implemented: an immune inspired algorithm and a fuzzy logic based algorithm. The immune inspired algorithm uses the human antigen as a model to represent the server power / performance state. Using a set of detectors the antigens are classified as self for optimal power consumption state or non-self for non-optimal power consumption state. For the non-self antigens a biologically inspired clonal selection approach is used to determine the actions that need to be executed to bring the server∂V�&38� in an optimal power consumption state. The fuzzy logic based algorithm adaptively changes the processor performance states to the incoming workload. The algorithm also filters workload spikes because frequent p-states transition costs can outweigh the benefit of adaptation.
