The Experts below are selected from a list of 255 Experts worldwide ranked by ideXlab platform

H.j. Shin - One of the best experts on this subject based on the ideXlab platform.

  • A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits
    IEEE Journal of Solid-State Circuits, 1994
    Co-Authors: H.j. Shin
    Abstract:

    A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the Emitter-Follower input from the logic stage. Simulation results based on a 0.5-/spl mu/m advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively.

  • Full-swing BiCMOS logic circuits with complementary Emitter-Follower driver configuration
    IEEE Journal of Solid-State Circuits, 1991
    Co-Authors: H.j. Shin
    Abstract:

    Various full-swing BiCMOS logic circuits with complementary Emitter-Follower driver configurations are described. The performance of the circuits is demonstrated in a 1.2 mu m complementary BiCMOS technology with a 6 GHz n-p-n and a 2 GHz p-n-p transistor. For the basic circuit, gate delay (fan-in=2, fan-out=1) is 366 ps and driving capability is 288 ps/pF at 4 V. Delay-power tradeoffs that depend on characteristics of the clamping diode between two base nodes of the complementary Emitter-Follower driver, parasitic capacitances at the two base nodes, and a technique that can be used to achieve full swing have been identified for these circuits. These circuits show leverage over the conventional BiCMOS circuit for reduced power-supply voltages. >

A. Maxim - One of the best experts on this subject based on the ideXlab platform.

Shin - One of the best experts on this subject based on the ideXlab platform.

  • Self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits
    Symposium on VLSI Circuits, 1993
    Co-Authors: Shin
    Abstract:

    The self-biased, feedback-controlled, active-pull-down emitter follower is a very efficient and superior circuit applicable to high-speed low-power bipolar/BiCMOS digital VLSIs. The circuit is effective because the biasing, inverting, level-shifting, and coupling functions are simply merged into a small number of devices and is versatile for logic implementations because it does not need any extra out-of-phase signal from the logic stage, allowing the collector-dotting and emitter-dotting. The push-pull operation of this novel circuit is precisely controlled by a feedback mechanism and results in a remarkable performance enhancement: 2.7x typical simulated pull-down speed and 10x drive capability over the conventional RPD-ECL.

Ching-te Chuang - One of the best experts on this subject based on the ideXlab platform.

  • 14.9 ps/2.2 mW charge-buffered active-pull-down ECL circuit
    Electronics Letters, 1992
    Co-Authors: K. Chin, Ching-te Chuang, James D. Warnock
    Abstract:

    An ECL circuit with a charge-buffered active-pull-down Emitter-Follower stage is described. Implemented in a 0.8 μm double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9 ps/2.2 mW, 20.7 ps/1.2 mW, and 24.5 ps/0.77 mW have been achieved.

  • NTL with complementary Emitter-Follower driver: a high-speed low-power push-pull logic circuit
    IEEE Journal of Solid-State Circuits, 1991
    Co-Authors: Ching-te Chuang
    Abstract:

    A high-speed low-power nonthreshold-logic (NTL)-based push-pull logic circuit, featuring a complementary Emitter-Follower driver is presented. Compared with the standard NTL circuit, the circuit offers a much better balance between the pull-up and pull-down delay, improved scalability, and superior load driving capability. Simulation results based on a 0.8- mu m double-poly. self-aligned complementary bipolar technology indicate that at a power consumption of 1.22 mW/gate, the circuit offers 2.4* improvement in the pull-down delay of a loaded gate and 4.0* improvement in the load driving capability over the standard NTL circuit. The design and scaling considerations of the circuit are discussed. >

Chikara Yamaguchi - One of the best experts on this subject based on the ideXlab platform.

  • Master-Slave Toggle Flip-Flop Circuit
    1994
    Co-Authors: K. Ishii, Haruhiko Ichino, Chikara Yamaguchi
    Abstract:

    This paper presents a propagation-delay equation which is expressed as the influence of the individual device and circuit parameters on the maximum operating frequency of Si bipolar master-slave toggle flip-flop (MS-TFF) circuit with double feedback emitter followers. This equation shows that optimizing the size of individual transistors can enhance the operating speed. Test results show a 10% increase in operating frequency by adopting this design technique. It is also shown that the time constants RBCJ(., RBC~, ~fi, RLC~C, and R,.CJ,- of the upper- level current switch and TI. of the second feedback emitter follower greatly affect the operating speed of circuits using recently developed Si bipolar transistors. The results predicted by the equation are in good agreement with both the experimental ones and SPICE simulations.

  • Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit
    IEEE Journal of Solid-State Circuits, 1994
    Co-Authors: K. Ishii, Haruhiko Ichino, Chikara Yamaguchi
    Abstract:

    This paper presents a propagation-delay equation which is expressed as the influence of the individual device and circuit parameters on the maximum operating frequency of Si bipolar master-slave toggle flip-flop (MS-TFF) circuit with double feedback emitter followers. This equation shows that optimizing the size of individual transistors can enhance the operating speed. Test results show a 10% increase in operating frequency by adopting this design technique. It is also shown that the time constants R/sub B/C/sub jC/, R/sub B/C/sub D/, T/sub F/, R/sub L/Cj/sub C/, and R/sub C/Cj/sub C/ of the upper-level current switch and T/sub F/ of the second feedback emitter follower greatly affect the operating speed of circuits using recently developed Si bipolar transistors. The results predicted by the equation are in good agreement with both the experimental ones and SPICE simulations. >